Cadence accelerates high-performance, giga-scale, 20nm design with next-generation Encounter RTL-to-GDSII flow

SAN JOSE, USA: Cadence Design Systems Inc. introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers.

Developed in close collaboration with leading IP and foundry partners and customers, the new RTL-to-GDSII design, implementation and signoff flow enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.

The new RTL-to-GDSII flow builds on established Cadence successes, further advancing its technology leadership in power, performance, and area for the world’s most advanced high-performance, low-power SoC designs. The flow is enabled by Encounter RTL Compiler, Encounter Test, Encounter ECO Designer, Encounter Digital Implementation System, Clock Concurrent Optimization (CCOpt), Encounter Timing System, Encounter Power System, Cadence QRC Extraction, Cadence Physical Verification System, and design for manufacturing technologies.

"The Cadence Encounter RTL-to-GDSII flow enabled us to achieve the chip performance and feature objectives of our 1 GHz ARM Cortex-A5 processor-based smartphone platform on time and with greater development efficiency," said Dr. Leo Li, president and CEO of Spreadtrum.

"The new flow, with features such as physical-aware synthesis and the GigaOpt engine, enables excellent power-performance-area trade-offs that support the development objectives for our complex designs at advanced process nodes. The 3G low-cost smartphone market in China is expected to experience ongoing rapid growth, and our smartphone platform is now well positioned to capture this market opportunity."

Technical details on high-performance design, implementation and verification will be discussed in detail at the CDNLive! Silicon Valley Cadence user conference March 13-14 in San Jose. Registration is open. Additional details about the latest Encounter digital flow also will be discussed in a series of Cadence-sponsored webinars.

The new Encounter 20-nanometer methodology delivers silicon-proven 20-nanometer capabilities with correct-by-construction double-patterning support, covering capabilities from floorplanning, placement and routing to signoff timing, power and physical verification. This approach improves die area efficiency of 20-nanometer double-patterning designs, and enables more efficient engineering change order (ECO) revisions. Enhancements to the Cadence Physical Verification System provide foundry-qualified 20-nanometer in-design checking and final signoff verification to ensure DRC and double patterning color correctness.

This latest release of the Encounter RTL-to-GDSII flow also includes the new GigaOpt engine, which uniquely integrates key physical-aware synthesis technology with physical optimization, enabling faster timing closure and better correlated results. It is a highly scalable optimization engine that supports designs featuring leading high-performance processors. By harnessing the power of multiple CPUs, the engine produces results much faster than traditional optimization engines.

In addition, the new differentiated CCOpt technology unifies clock tree synthesis with physical optimization, resulting in up to 10 percent improvement in design performance, and up to 30 percent reduction in clock tree power and area.

Another key element of the release is GigaFlex technology, a new capability that greatly expands the capacity to handle today’s largest designs of 100 million instances or more. Designers can now achieve full-chip design prototyping goals in just 10 percent of the time required previously, enabling them to uncover potential issues earlier to produce the optimal design floorplan sooner.

The GigaFlex technology enables concurrent top-and-block hierarchical design and implementation, reducing iterations and total design cycle time by an order of magnitude. In addition, automated functional ECO technologies accelerate pre- and post-mask ECO changes, which are reduced to hours or days through smart hierarchical design handling.

“We continue to collaborate very closely with our IP and foundry partners and customers to advance our technologies to address the challenges of the high-performance, giga-scale chips at the most advanced geometries,” said Dr. Chi-Ping Hsu, senior VP, research and development, Silicon Realization Group at Cadence. “We are once again demonstrating our commitment to delivering leading technology required to enable the most advanced designs using the most advanced processes.”