Cosmic Circuits selects Berkeley Design Automation AFS Nano

SANTA CLARA, USA: Berkeley Design Automation Inc., a provider of the Analog FastSPICE unified circuit verification platform announced that Cosmic Circuits, a leading provider of differentiated high-performance analog and mixed-signal intellectual property (IP) for nanometer silicon processes, has selected the company's Analog FastSPICE Nano SPICE simulator (AFS Nano) for IP core verification.

"Cosmic Circuits' designs go through rigorous checks at the simulation level before being committed to silicon," said Ganapathy Subramaniam, CEO of Cosmic Circuits. "AFS Nano reduces simulation time by a factor of 5-10x compared to traditional SPICE with identical results. With this performance we can thoroughly characterize PLLs, ADC blocks, and DACs, for process variability resulting in faster delivery of high quality IP cores to our customers."

Analog FastSPICE is the industry’s only unified circuit verification platform for analog, mixed-signal, and RF design. Always delivering true SPICE accurate results, it provides 5x-20x higher performance than traditional SPICE, >10 million-element capacity, and the industry’s only comprehensive noise analysis.

The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the full-circuit matrix and original device equations without any shortcuts. AFS Platform tools include: AFS Nano SPICE simulator, Analog FastSPICE circuit simulator, Noise Analysis Option device noise analyzer, and RF FastSPICE multi-tone periodic analyzer.

"We are excited that Cosmic Circuits has selected AFS Nano for their IP verification and characterization," said Ravi Subramanian, president and CEO of Berkeley Design Automation.

"Cosmic Circuits’ silicon IP for nanometer process nodes requires expert analog designers, a strong focus on analog architectures to combat variability, and the right tools for the job. Cosmic Circuits' selection of AFS Nano further validates the strong competitive advantage the Analog FastSPICE Platform provides to leading-edge analog/mixed-signal IP designers."

Cosmic Circuits tapes out 40nm mixed signal test chip

BANGALORE, INDIA: Cosmic Circuits, a leading provider of differentiated Analog and Mixed-Signal IP cores, announced the tape out of its TSMC 40nm mixed signal test chip.

The test chip consists of several data converters and power regulators for Wireless Communications and Portable consumer applications. A/D and D/A converters that are used in the baseband section of wireless communication chips for applications such as MIMO WLAN 802.11n and WiMAX are included in this test chip, along with the low jitter PLLs.

The A/D Converters range from 8-10 bit resolutions at 20-80 MHz sampling rate and D/A Converters’ specification are 8-bit / 20MHz and 12-bit / 160MHz. Also included are Switching and Linear Power-Regulator cores that help optimize battery life and reduce BOM cost in Portable consumer applications.

C. Srinivasan, VP of engineering at Cosmic Circuits, said: “The data converter cores are designed using a unique amplifier-less architecture that is friendly to nanometer process technologies. We continue to innovate in order to bring low- power cores that are also compact, making it suitable for Wireless MIMO applications.”

He added, “On the power regulators front, we have brought our silicon proven architecture into 40nm, including a DC-DC Switching regulator that is capable of connecting directly to a Lithium ion battery and a high performance LDO Linear Regulator suitable for powering sensitive analog circuitry.”

“This demonstrates Cosmic Circuits’s commitment to bringing complex and differentiated Analog IP cores to the market, now in cutting edge 40nm technology node” said Krishnan Ramabadran, VP of Marketing for Cosmic Circuits. “These cores address the critical need for power reduction and system cost optimization as Wireless and portable consumer markets progress to the 40nm node.

These cores, while being differentiated, have been designed keeping in mind several practical considerations that arise in SoC environment effectively addressing the end success of any SoC customer’s chip development. Specific needs to multi channel MIMO applications are catered through flexible customization.

Cosmic Circuits constantly endeavors to bring differentiated and quality Analog and Mixed-Signal IP cores to the design-community for integration on system-on-Chips. Through its portfolio of high-performance cores, the company helps its customers accelerate time-to-market, while covering the Analog integration requirements. Cosmic Circuits provides excellent support by staying engaged during the entire development cycle, through production ramp.

Chartered begins production ramp of enhanced 65nm low-power process

SINGAPORE: Chartered Semiconductor Manufacturing announced the general availability of an enhanced version of its 65nm low-power (LP) process, called 65nm LPe.

The 65nm LPe process utilizes innovative leakage-reduction techniques to significantly improve system-on-chip (SoC) standby power consumption by up to 50 percent.

The result is a lower-power process especially suited for battery-operated and cost-sensitive mobile applications that require active standby conditions, such as mobile handsets, multimedia players or personal internet devices. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.

Chartered is also offering an optimized RF platform solution based on the 65nm LPe process that combines RF physical design kits, broad IP support and a collaborative development system with its partners from the Wireless SoC Platform Alliance (WISPA) consortium. (See additional press release from July 13, 2009: “Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless Applications”).

The 65nm LPe process significantly improves the performance-to-leakage ratio (Ion/Ioff) within the process’ pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by a magnitude of 20X.

This directly impacts the battery life of mobile applications as this leakage improvement is observable in both active and standby situations. In cases where a product operates in long standby situations such as a mobile phone, improvement in the standby power consumption can be as great as 15-25 percent, depending on the application.

A full suite of IP is available for the new process from leading suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic Circuits, Denali, Synopsys, True Circuits and Virage Logic.

The support includes analog front end (AFE), audio codecs, standard interfaces and a range of level physical IP libraries and memory compilers that have been specifically tuned to take advantage of the enhanced leakage capabilities of the process.

Chartered’s enhanced 65nm LPe process features a core 25 angstrom transistor oxide with three voltage options (Standard Vt, Low Vt, High Vt). The High Vt option offers the lowest leakage at 0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors, respectively.

Two thick gate oxides are available: a 32A device for 1.8V; and a flexible, IP-enabled 2.5V 52A device that is also useable for 1.8V and 3.3V applications by varying the channel length. The back end of line (BEOL) metal implementation supports up to nine layers of copper to optimize die size and routing efficiency.

Manufactured on rotated substrates, the 65LPe process benefits from an increase in the pMOSFET hole mobility and saturation velocity without detrimentally affecting the nMOSFET.

“Today’s high-volume mobile applications require highly optimized silicon solutions that operate in an extremely power-efficient manner, but don’t compromise performance or functionality,” said Brian Klene, vice president, product marketing at Chartered.

“Our 65nm LPe process has been developed specifically with extended battery life in mind, with optimizations made to the process itself and our ecosystem of design support to improve efficiency significantly. The 65nm LPe process is a full-featured and flexible platform on which a wide variety of wireless, mobile and multimedia products can be based.”

Karnataka semicon policy very soon!

The government of Karnataka will be announcing a semiconductor policy very soon, according to Katta Subramanya Naidu, the minister for Excise, Information, BWWB, IT and BT, government of Karnataka, while delivering the opening address at the ISA Excite organized by the India Semiconductor Association.

Over the last several years, India has been a destination favored by almost all leading global semiconductor companies for setting up their development centers for semiconductors and embedded designs.

The size of the Indian semicon design industry is currently $6 billion across VLSI and board design, and embedded software, with the potential to be around $9 billion by 2009. There are nearly 200 companies and it employs over 130,000 professionals, all over India, with the potential to employ over 180,000 by 2009. The Indian semicon design industry has a CAGR of nearly 22 percent versus the global average of 7-8 percent.

Nearly 90 percent of the VLSI design work is done out of Bangalore alone. Appropriately, the ISA is headquartered in Bangalore, the heart of India's chip industry. The minister said: "The conducive work environment policies and high-quality talent are the important attractions for both MNCs and Indian companies to set up shop here. We value the contribution of our technology leaders and engineers to build the economy of the state and make it a global leader. Bangalore is next only to Silicon Valley, California, in terms of the work done here."

New centers likely
In future, the government of Karnataka wants to look at Mysore, Mangalore and Hubli as important centers to be developed. "These are centers of education with high quality and quantity of engineering talent. Our government is working on improving the connectivity to these cities to help attract investment there, as well as the expansion of companies from Bangalore to other towns within Karnataka," he added.

Welcome the ISA initiative to launch Excite, a program for the semiconductor and ecosystem companies, he noted that it was a good platform to understand the technology trends and to collaborate with the right partner.

He said: "Karnataka today is at the crossroads. We have the direction and leadership of Hon'ble chief minister Yeddyruppa. He is extremely committed to the cause of making Karnataka as the most preferred destination for the semiconductor industry and electronics hardware manufacturing. My (BJP) government would be glad to extend any support for your business plans in the state."

Semicon policy soon
The state government plans to announce a semiconductor policy in the very near future, actually. It has also earmarked land for a hardware technology park near the new airport (in Devanahalli).

The government is also thinking in the lines of finishing schools in PPP mode as the semiconductor industry is technology driven, and demands continuous training and re-skilling of the workforce.

Initiatives in Karnataka
The minister pointed out that his government has been taking several pro-active steps for further accelerating the growth of these sectors, as well as for their expansion in tier II and III cities. For these two sectors, the government proposes to identify and set apart exclusive IT/BT zones in Mysore, Mangalore, Hubli-Dharwad, Belgaum, Shimoga and Gulbarga.

Yeddyruppa, the state chief minister, has made an announcement of a number of initiatives to boost the growth and development of IT/BT. A bio-IT park on a 100-acre plot is proposed to be developed with private participation near Bangalore. IT parks, with private participation, would be set up in tier II and III cities. A massive IT city on the lines of the Electronics City near Bangalore is under consideration. Similarly, BT parks are proposed to be set up in Mangalore, Dharwad and Bidar. KEONICS, a government of Karnataka undertaking, will play a major role in development of the IT city, IT parks and computer literacy campaigns.

He added that the state government believes in formulating initiatives and policies in consultation with the industry. The existing Mahithi IT policy is also being revised with inputs from the Vision Group on IT headed by N.R. Narayana Murthy of Infosys.

"The state government would be happy to see IT and BT developments happening in tier II and III cities. We are taking steps to improve and upgrade the infrastructure in these cities. The CM is personally reviewing the construction and upgradation of airports in Mysore, Shimoga and Gulbarga, which will provide vital air connectivity, essential for the growth of industry and business," he noted.

The NASSCOM-Kearney report has identified 43 potential locations in the country for IT development. The report also suggests measures to be taken to make these locations attractive for IT investments. Recommendations, such as improving the quality of education, imparting employable skills to the uneducated youth, improving infrastructure, particularly, air connectivity, etc., would be taken into consideration.

The minister said: "Our government would take all the necessary steps to ensure that there is no flight of investment to other states, and to make Karnataka the most attractive region for IT/BT investments. We want the semiconductor industry to grow and flourish in the state."

Participative semicon policy likely
Elaborating on the proposed semiconductor policy for Karnataka, Ashok Kumar C. Manoli, principal secretary to the government, said: "When you look at India, it is software, and when you look at China, it is hardware. We should make a beginning and try and become the global capital for both hardware and software. We need to design such a policy that design activities continue and also facilitate manufacturing."

He added: "We will come up with a very participative semiconductor policy. It will also look at addressing infrastructure requirements for manufacturing setups." According to him, the hardware industry is the foundation for the entire revolution, which the government is looking at. He requested all companies present at the ISA Excite to participate at the forthcoming BangaloreIT.com event, and added that the state government was committed and fully geared up to deliver.

Announcing the ISA Excite initiative, Sanjeev Keskar, country sales manager, Freescale Semiconductor India Pvt Ltd, said: "We need to collaborate with the right partner. The ISA felt the need to arrange an ecosystem meet. Telecom and healthcare are the two drivers of importance." The ISA has plans to take Excite to other cities too, possibly, New Delhi, focusing on industrial and consumer.

The one-day ISA Excite event had an exhibition running simultaneously, featuring about 40 companies. These included ARM, Farnell, Ittiam Systems, Broadcom, Cosmic Circuits, Windriver, Wipro, HCL, AMDL, LSI Logic, TI, NXP, Cisco, Synopsys, SemIndia, Freescale, Open Silicon, MindTree, AMD, Analog Devices, RFMD, Cir-Q-Tech, NewEra, STPI, etc.