WILSONVILLE, USA: Mentor Graphics Corp. announced its newest version of the Mentor Embedded Hypervisor product offering advanced features for system configuration, debugging, and hardware support for developing robust, reliable, and secure applications.
This solution enables high-performance applications for industrial, medical, automotive, networking, telecommunications and consumer electronics products.
The new Mentor Embedded Hypervisor product provides data-driven configuration and device trees for guest resource partitioning instead of hard-coded guest resource tables contained in each board support package. This enables easier system build and configuration. Binary image generation can now be easily deployed on the target hardware.
Debugging enhancements include: a simpler command syntax and more extensible design capabilities; JTAG debugging for the hypervisor and guest operating systems; and tighter integration with the Sourcery CodeBench integrated development environment (IDE) for synchronized system tracing in a single analysis to identify problems and performance bottlenecks.
Today’s complex heterogeneous System on Chip (SoC) architectures increasingly combine application class cores alongside microcontroller-class cores, driving the consolidation of complex heterogeneous operating environments on a single device.
As devices become more complex, an asymmetric multi-processing (AMP) framework based on embedded virtualization technology is required to manage the challenges associated with inter-process communication (IPC), resource sharing, and processor control within a heterogeneous multi-OS environment.
This new release delivers an efficient and scalable IPC mechanism (based on technology found in most Linux® operating system distributions), extended for multicore and multi-OS scenarios, including a clean-room implementation to support it.