SAN JOSE, USA: Cadence Design Systems Inc. announced that its digital and custom/analog tools have achieved V0.9 Design Rule Manual (DRM) and SPICE certification from TSMC for its 16FF+ process.
This will enable systems and semiconductor companies to take advantage of the 15 percent speed improvement with the same total power compared to 16nm FinFET, or 30 percent total power reduction at the same speed compared to 16nm FinFET. 16FF+ V1.0 certification is on track to be concluded by November 2014.
Cadence also collaborated with TSMC to make several enhancements to its Custom Design Reference Flow (CDRF) for the 16FF+ process. Additionally, Cadence and TSMC are collaborating on the 10nm FinFET process, and Cadence solutions are ready to support 10nm early customer design starts.
The Cadence custom/analog and digital implementation and signoff tools have been validated by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure. Cadence tools certified for 16FF+ include Encounter® Digital Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus QRC Extraction Solution, Virtuoso® custom design platform, Spectre simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor.
Enhancements to the CDRF include an exclusive TSMC application programming interface (API) incorporated into Virtuoso Analog Design Environment GXL that speeds up statistical simulation flow, a new design methodology leveraging module generator (ModGen) technology for designing FinFET arrays to avoid density gradient effects, and the introduction of the electrically aware design (EAD) platform to extract and analyze real-time parasitics and electromigration (EM) violations during design implementation.
Cadence tools in the flow include Virtuoso custom design platform, Integrated Physical Verification System, Physical Verification System, Quantus QRC Extraction Solution, Spectre simulation platform, Voltus-Fi Custom Power Integrity Solution and Litho Electrical Analyzer.
Cadence also announced today a broad portfolio of intellectual property (IP) for TSMC's 16nm FinFET Plus (16FF+) process.