SAN JOSE, USA & CAMBRIDGE, ENGLAND: Cadence Design Systems Inc. and ARM announced the signing of a multi-year Technology Access Agreement.
Expanding upon the successful EDA Technology Access Agreement signed in May 2014, this new agreement gives Cadence rights to access to existing and future ARM Cortex processors, ARM Mali GPUs, ARM CoreLink System IP, ARM Artisan physical IP, and ARM POP IP.
This partnership enables ARM and Cadence to continue providing customers with advanced low-power and high-performance system-on-chip (SoC) design solutions for markets including next-generation mobile, consumer, networking, storage, automotive and IoT.
"Together, ARM and Cadence have delivered robust solutions that have enabled developers, designers and engineers to create innovative new ARM-based devices," said Pete Hutton, executive VP and president of product groups, ARM. "This new agreement is a strong commitment from both companies to continue delivering the key technologies and tools the design community needs when creating world-class products and pushing the boundaries of innovation."
Additional features of the agreement include the ability for Cadence to develop optimized processor scripts and flows for Mali GPUs and the latest high performance ARM processors, including the recently announced ARM Cortex-M7 core for embedded applications.
The collaboration between Cadence and ARM on the Cortex-M processor family leverages Cadence's proven integrated mixed-signal design and verification flow and expertise in low-power design and verification for applications including IoT end-node device implementation. Early access to Artisan Physical IP enables Cadence to optimize its physical design tools to achieve aggressive power, performance and area targets.
The agreement also complements the previously existing collaborations between ARM and Cadence around implementation and verification of ARM's 64-bit ARMv8 architecture Cortex-A50 processor series, the integration of ARM Fast Models with Cadence Palladium XP series hardware for fast hybrid virtual emulation, and performance verification and analysis for CoreLink 400 interconnect IP-based systems using Cadence's Interconnect Workbench solution.