MOUNTAIN VIEW, USA: Synopsys Inc. announced that TSMC has certified a comprehensive list of Synopsys' custom and digital design tools for their 16-nm FinFET+ processes.
The V0.9 certifications are all completed and V1.0 certification is on-track and to be concluded by November, 2014. The two companies have also entered N10 collaboration. With needed tool enhancements in place to meet 10-nm FinFET process requirements, customers can now use Synopsys tools for their 10-nm design starts.
Collaboration between TSMC and Synopsys is enabling customers to deploy Synopsys' industry-leading digital and custom tools to take advantage of the power, performance and area benefits of the 10-nm and 16-nm process technologies.
The extensive engineering collaboration between Synopsys and TSMC facilitated delivery of key technologies including routing rules, physical verification runsets, extraction technology files, interoperable process design kits (iPDKs) and a reference flow for the N16FF+ process. System-on-Chip (SoC) design teams can now deploy the silicon-proven, project-ready Synopsys solution to implement FinFET-based designs.
"Our deep and extensive collaboration with Synopsys on critical design-enablement technologies has continued beyond the N16FF process," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division at TSMC. "Jointly, Synopsys and TSMC are addressing our customers' needs to deliver highly optimized design solutions for N10FF and N16FF+ process geometries."
"Our goal is to enable our mutual customers to maximize the power, performance and area benefits of the 10nm and 16-nm FinFET process technologies," said Bijan Kiani, VP of product marketing, Design Group, at Synopsys. "This extensive technology collaboration spans the digital and custom tools to allow engineers to deliver their next-generation designs in a productive and predictable manner."