HENDERSON, USA: Aldec Inc., a leader in RTL simulation and EDA, unveiled a new low-cost mixed language RTL simulator -- Active-HDL Designer Edition.
The product closes a gap in the mixed RTL FPGA simulation market. Today, FPGA designers can purchase a high performance mixed language RTL simulator from Aldec or other commercial EDA vendors starting at $6,000 or alternatively purchase a restricted, single language, FPGA vendor supplied simulator for $1,000 or less.
A price, feature and performance gap exists between the commercial EDA simulators and the FPGA vendor simulators. Active-HDL Designer Edition fills this market gap and provides FPGA designers with a mixed language simulator for less than $2,000.
The product includes: industry proven IEEE mixed-language simulation support for VHDL, Verilog and SystemVerilog (Design), 2X-plus performance gains over FPGA vendor supplied RTL simulators, encrypted IP support and no performance limitations on FPGA design size.
By purchasing Active-HDL Designer Edition, FPGA designers receive technical support directly from the EDA manufacturer.
Additionally, software revisions and library maintenance are the same across all configurations of Active-HDL providing a smooth upgrade path if additional functionality is required. Capabilities such as code coverage, design rule checking, DSP modeling and verification, SystemC co-simulation, transaction level modeling or assertion based verification are available.
Active-HDL Designer Edition is available today and supports Windows 32/XP/Vista operating systems. The product is offered as a one year time based license and available as either a node locked ($1,995) or floating ($2,495) license.