SAN DIEGO & NEWPORT BEACH, USA: The University of California, San Diego (UCSD), provider of a leading program in microwave and millimeter-wave RFICs and mixed-signal, and Jazz Semiconductor, a Tower Group Company have collaborated to develop a two-antenna quad-beam RFIC phased array receiver covering the 11-15GHz frequency range.
First time success was achieved using Jazz Semiconductor’s high performance 0.18-micron SiGe BiCMOS process and its own proprietary models, kit and DIRECT MPW (Multiproject Wafer) program. The chip was designed and tested by the Electrical and Computer Engineering School at UCSD, and was sponsored by the DARPA RF VLSI program, Dr. Mark Rosker, Program Monitor.
“UCSD believes that the quad-beam phased array receiver will enable high-performance phased arrays for satellite communications by integrating many functions on the same silicon chip and replacing several GaAs ICs, drastically lowering the cost of phased array assembly,” said Dr. Gabriel M. Rebeiz, Professor of Electrical Engineering at UCSD, a co-developer of this chip.
“Our success in developing this first-of-a-kind chip depended largely on Jazz’s 0.18-micron SiGe BiCMOS process, models and design kit. We view Jazz as a leading specialty foundry with unrivaled design enablement capabilities.”
This is the first demonstration of a single silicon chip capable of producing four simultaneous beams from two different antennas, and together with all the necessary CMOS controlling circuits. Alternatively, this chip can be connected to a single antenna with two different polarization ports, thereby allowing the formation of four simultaneous beams of different polarizations.
The four simultaneous phased-array beams can be all at the same frequency, or placed randomly at any frequency in the 11-15 GHz range. Each beam can operate over an instantaneous bandwidth of > 1 GHz with 4-bit amplitude and phase control.
As the chip creates four simultaneous beams from the antennas, these beams can point to different areas in the sky (i.e. different angles), preventing the signal gathered in beam 1 to couple to beam 2, and enables at least 30 dB isolation between the two beams.
The SiGe BiCMOS chip operates from a 3.3 V supply, is only 2.4x4.3 mm2, replaces at least 8 GaAs chips, and allows a new generation of high-performance multi-beam phased arrays for X to Ku-Band applications.
The SBC18HX process offers high-performance 0.18-micron SiGe bipolar and high quality passive elements combined with high density 0.18-micron CMOS, ideal for high-speed networking and millimeter wave applications. This leading edge process achieves an Ft of 155GHz and an Fmax of 200GHz.
"We are pleased with the results achieved by UCSD with its RFIC quad-beam phased array receiver and are excited to enable an innovative technology designed to address the needs of high data-rate communications and satellite-based systems markets,” said David Howard, Executive Director of New Product Technology at Jazz Semiconductor.
“This collaboration demonstrates the capabilities of the highly advanced specialty wafer processes, models and kits we offer to our customers.”
“The chip is currently being transitioned by the US Office of Naval Research to a 1000+ element phased-array capable of four simultaneous beams at Ku-Band, and a contract to a leading US defense company was recently issued based on this chip,” added Dr. Rebeiz.
The chip is available from UCSD and interested parties should contact Prof. Gabriel M. Rebeiz; Department of Electrical and Computing Engineering at UCSD.
Friday, July 3, 2009
Thursday, July 2, 2009
MosChip, IdealBT to offer NAS network appliance processor and system software solution
SANTA CLARA, USA: MosChip Semiconductor Technology Ltd., a leading provider of high performance connectivity solutions for consumer, industrial and computing applications, has entered into a technology partnership with IdealBT Technology Corp. to bring to market a complete system solution for network attached storage (NAS) applications.
MosChip’s System-on-a-Chip (SoC) devices cover a myriad of NAS design requirements while IdealBT’s embedded Linux-based software has been designed into numerous functional, versatile, high-performance, and reliable NAS solutions.
MosChip’s family of SoC network appliance processors (NAP) for NAS includes the MCS8140, MCS8142 and MCS8144. They are based on an enhanced ARM9 processor designed to deliver best in class performance with complete system solutions, including evaluation systems, support for Linux and Win CE operating systems, firmware and application level software to enable quick time to revenue. The offering enables immediate production, reduces design time and design investments while effectively controlling bill-of-materials costs.
The devices are highly integrated NAPs with Gigabit Ethernet, PCIe, USB, DDR-II memory interface and other key features supported. With advanced CPU performance, support for compute intensive applications without compromising system
performance is made possible. PCIe can be supported in single or dual mode for scalable performance.
The devices can also provide a point-to-point link to each device on the system bus, low latency, and Quality of Service (QoS) to enable guaranteed bandwidth. Additional external WLAN and storage options are also supported through the USB
and PCIe interfaces. Gigabit Ethernet support comes with hardware acceleration enabling TCP/IP/UDP. Segmentation off-load and IP Checksum off-load allows higher performance at optimal CPU load.
Combined with IdealBT’s system software based on embedded Linux, system designers will find MosChip’s devices ideal as a processor to enable system processing, networking connectivity, to support additional devices through USB, and to support display-based devices. IdealBT’s system software provides basic NAS functions, advanced services and tools. Basic functionalities include LAN and system support; user and folder management; and multilanguage support.
Services supported include: FTP, Samba support; BT; UPnP AV; iTunes®, backups; and printer functions. Tools offered will include: restart, HDD formatting; firmware upgrades; configuration saves; factory default settings; login settings; email sending; and a system log. There is also the ability for UI and functions customizations, mass production tools and NAS discovery tools. MosChip and IdealBT’s combined solutions are aimed at supporting MosChip’s MCS8142 and MCS8144 devices.
“Our embedded Linux platforms are ideal for a wide range of NAS solutions and provide advanced system software
capabilities to expedite time to market,” commented William Chiu, CEO for IdealBT Technology Corp. “Our partnership with MosChip will help embedded NAS designers in their efforts to reduce design time and costs while still bringing to market the strong NAS solutions demanded by end customers.”
“Today’s embedded designers are looking for more than just a device that can do NAS functions,” added Vamshi Kandalla, VP of Marketing for MosChip Semiconductor. “It is important to also offer the option of providing a complete embedded solution. In this way, time to market and revenue can be expedited. Our partnership with IdealBT is centered on this theme for a variety of Linux-based high performance NAS solutions.”
MosChip’s System-on-a-Chip (SoC) devices cover a myriad of NAS design requirements while IdealBT’s embedded Linux-based software has been designed into numerous functional, versatile, high-performance, and reliable NAS solutions.
MosChip’s family of SoC network appliance processors (NAP) for NAS includes the MCS8140, MCS8142 and MCS8144. They are based on an enhanced ARM9 processor designed to deliver best in class performance with complete system solutions, including evaluation systems, support for Linux and Win CE operating systems, firmware and application level software to enable quick time to revenue. The offering enables immediate production, reduces design time and design investments while effectively controlling bill-of-materials costs.
The devices are highly integrated NAPs with Gigabit Ethernet, PCIe, USB, DDR-II memory interface and other key features supported. With advanced CPU performance, support for compute intensive applications without compromising system
performance is made possible. PCIe can be supported in single or dual mode for scalable performance.
The devices can also provide a point-to-point link to each device on the system bus, low latency, and Quality of Service (QoS) to enable guaranteed bandwidth. Additional external WLAN and storage options are also supported through the USB
and PCIe interfaces. Gigabit Ethernet support comes with hardware acceleration enabling TCP/IP/UDP. Segmentation off-load and IP Checksum off-load allows higher performance at optimal CPU load.
Combined with IdealBT’s system software based on embedded Linux, system designers will find MosChip’s devices ideal as a processor to enable system processing, networking connectivity, to support additional devices through USB, and to support display-based devices. IdealBT’s system software provides basic NAS functions, advanced services and tools. Basic functionalities include LAN and system support; user and folder management; and multilanguage support.
Services supported include: FTP, Samba support; BT; UPnP AV; iTunes®, backups; and printer functions. Tools offered will include: restart, HDD formatting; firmware upgrades; configuration saves; factory default settings; login settings; email sending; and a system log. There is also the ability for UI and functions customizations, mass production tools and NAS discovery tools. MosChip and IdealBT’s combined solutions are aimed at supporting MosChip’s MCS8142 and MCS8144 devices.
“Our embedded Linux platforms are ideal for a wide range of NAS solutions and provide advanced system software
capabilities to expedite time to market,” commented William Chiu, CEO for IdealBT Technology Corp. “Our partnership with MosChip will help embedded NAS designers in their efforts to reduce design time and costs while still bringing to market the strong NAS solutions demanded by end customers.”
“Today’s embedded designers are looking for more than just a device that can do NAS functions,” added Vamshi Kandalla, VP of Marketing for MosChip Semiconductor. “It is important to also offer the option of providing a complete embedded solution. In this way, time to market and revenue can be expedited. Our partnership with IdealBT is centered on this theme for a variety of Linux-based high performance NAS solutions.”
Ready for the surge? IC Insights' 2H09/1H09 forecast
Worlwide IC market +18 percent; IC foundry sales +43 percent; semiconductor capital spending +28 percent
USA: According to IC Insights' soon-to-be-released Mid-Year Update to The McClean Report, 2009 is forecast to be a "tale of two halves."
The first half of 2009 was hit hard by seasonal weakness for electronic system sales, a major IC inventory adjustment, and the global recession at its worst (with the global economy registering a rare drop in GDP).
However, the second half of 2009 is expected to usher in strong seasonal strength for electronic system sales, a period of IC inventory replenishment (which began in 2Q09), and positive worldwide GDP growth.
In IC Insights' opinion, the bottom of the current cycle in the worldwide economy and semiconductor industry was reached in 1Q09. While the "velocity" of the semiconductor industry recovery is subject to debate (slow, moderate, fast, etc.), at least the discussion over the next few quarters will be about how much sequential growth can be expected in instead of how far the markets are going to fall.
Since the beginning of this severe downturn, which began nine months ago, IC Insights has encouraged its clients to think quarterly about 2009, or in this case, at least in halves.
When doing so, a much more relevant and positive outlook of the business conditions for the remainder of this year is achieved as compared to the "less granular" annual viewpoint taken by most of the other industry forecasters.
Fig. 1 shows eight important examples where the second half of 2009 is expected to be much better than the first half of the year. Some key findings described in the Mid-Year Update to The McClean Report include:
* Worldwide GDP growth is forecast to be negative this year (-0.8 percent), but the second half of the year is expected to register positive growth. The same pattern is forecast for the US economy as well.
* IC Insights expects China's second-half GDP to climb almost 9 percent. In fact, China GDP growth in 4Q09 is forecast to be well over 9 percent!
* Seasonal strength is likely to propel 2H09 cellphone and PC unit shipments up by 18 percent and 15 percent, respectively, as compared to 1H09.
* The seasonal second-half jump in electronic system sales this year, coupled with stable and increasing IC average selling prices, is forecast to spur an 18% surge in the IC market in 2H09. In fact, the double-digit 2Q09/1Q09 IC market increase is clear evidence of the fact that the much-anticipated turning point has already occurred!
* The IC foundry market is expected to continue its sharp recovery in the second half of 2009. It should be noted the IC foundry market almost doubled in 2Q09 as compared to 1Q09!
* There is no doubt that, as a group, the semiconductor equipment suppliers have taken the worst "beating" of any of the companies involved in the current semiconductor industry downturn. However, the second half of 2009 is expected to offer some relief for these suppliers as semiconductor industry capital spending is forecast to jump by 28 percent as compared to the first half of 2009. As discussed in the Mid-Year Update to The McClean Report, many of the major semiconductor suppliers that IC Insights tracks are planning to spend the majority of their capital spending budgets in the second half of 2009 (e.g., Hynix spent 30 percent of its 2009 spending budget in 1H09 but plans to spend the remaining 70 percent in 2H09).
Most forecasters continue to resist calling for better growth in 2H09, perhaps unaware of the large amount of quarterly data that points to positive growth through the remainder of the year. IC Insights' Mid-Year Update to The McClean Report details why it believes that the 2H09 IC market is poised to surge ahead and mark the beginning of a strong multi-year growth period.
Source: IC Insights
USA: According to IC Insights' soon-to-be-released Mid-Year Update to The McClean Report, 2009 is forecast to be a "tale of two halves."
The first half of 2009 was hit hard by seasonal weakness for electronic system sales, a major IC inventory adjustment, and the global recession at its worst (with the global economy registering a rare drop in GDP).
However, the second half of 2009 is expected to usher in strong seasonal strength for electronic system sales, a period of IC inventory replenishment (which began in 2Q09), and positive worldwide GDP growth.
In IC Insights' opinion, the bottom of the current cycle in the worldwide economy and semiconductor industry was reached in 1Q09. While the "velocity" of the semiconductor industry recovery is subject to debate (slow, moderate, fast, etc.), at least the discussion over the next few quarters will be about how much sequential growth can be expected in instead of how far the markets are going to fall.
Since the beginning of this severe downturn, which began nine months ago, IC Insights has encouraged its clients to think quarterly about 2009, or in this case, at least in halves.
When doing so, a much more relevant and positive outlook of the business conditions for the remainder of this year is achieved as compared to the "less granular" annual viewpoint taken by most of the other industry forecasters.
Fig. 1 shows eight important examples where the second half of 2009 is expected to be much better than the first half of the year. Some key findings described in the Mid-Year Update to The McClean Report include:
* Worldwide GDP growth is forecast to be negative this year (-0.8 percent), but the second half of the year is expected to register positive growth. The same pattern is forecast for the US economy as well.
* IC Insights expects China's second-half GDP to climb almost 9 percent. In fact, China GDP growth in 4Q09 is forecast to be well over 9 percent!
* Seasonal strength is likely to propel 2H09 cellphone and PC unit shipments up by 18 percent and 15 percent, respectively, as compared to 1H09.
* The seasonal second-half jump in electronic system sales this year, coupled with stable and increasing IC average selling prices, is forecast to spur an 18% surge in the IC market in 2H09. In fact, the double-digit 2Q09/1Q09 IC market increase is clear evidence of the fact that the much-anticipated turning point has already occurred!
* The IC foundry market is expected to continue its sharp recovery in the second half of 2009. It should be noted the IC foundry market almost doubled in 2Q09 as compared to 1Q09!
* There is no doubt that, as a group, the semiconductor equipment suppliers have taken the worst "beating" of any of the companies involved in the current semiconductor industry downturn. However, the second half of 2009 is expected to offer some relief for these suppliers as semiconductor industry capital spending is forecast to jump by 28 percent as compared to the first half of 2009. As discussed in the Mid-Year Update to The McClean Report, many of the major semiconductor suppliers that IC Insights tracks are planning to spend the majority of their capital spending budgets in the second half of 2009 (e.g., Hynix spent 30 percent of its 2009 spending budget in 1H09 but plans to spend the remaining 70 percent in 2H09).
Most forecasters continue to resist calling for better growth in 2H09, perhaps unaware of the large amount of quarterly data that points to positive growth through the remainder of the year. IC Insights' Mid-Year Update to The McClean Report details why it believes that the 2H09 IC market is poised to surge ahead and mark the beginning of a strong multi-year growth period.
Source: IC Insights
Virage Logic expands India presence with broad IP portfolio, CorelEL as sales rep
FREMONT, USA: Virage Logic Corp. has expanded its presence in India with the appointment of CoreEL as its sales representative. CoreEL joins a growing global network of sales representatives that complement and expand the reach of Virage Logic’s direct sales channel.
CoreEL’s more than 15 years experience working with India’s networking, telecom, computing, consumer, industrial, defense and automotive customers make them ideally suited to represent Virage Logic’s broad portfolio of silicon proven IP.
“As the semiconductor industry continues to globalize and more semiconductor companies rely on their India-based teams to make SoC design project decisions, the time was right to bring CoreEL on board to service our growing India customer base,” noted Jai Iyer, Virage Logic’s vice president of Asia sales.
“We are confident that the combination of CoreEL’s strong technology and design services experience will enable them to provide the superior sales and support services Virage Logic’s customers worldwide have come to expect.”
“India is rich in engineering talent and a target for companies worldwide to tap into the engineering resources,” said Vishwanath Padur, vice president of Sales and Marketing for CoreEL.
“With Virage Logic’s highly differentiated IP offering -– including embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and interface IP solutions -– we look forward to being able to provide even greater value to our extensive customer base as we help them address their SoC design challenges.”
CoreEL’s more than 15 years experience working with India’s networking, telecom, computing, consumer, industrial, defense and automotive customers make them ideally suited to represent Virage Logic’s broad portfolio of silicon proven IP.
“As the semiconductor industry continues to globalize and more semiconductor companies rely on their India-based teams to make SoC design project decisions, the time was right to bring CoreEL on board to service our growing India customer base,” noted Jai Iyer, Virage Logic’s vice president of Asia sales.
“We are confident that the combination of CoreEL’s strong technology and design services experience will enable them to provide the superior sales and support services Virage Logic’s customers worldwide have come to expect.”
“India is rich in engineering talent and a target for companies worldwide to tap into the engineering resources,” said Vishwanath Padur, vice president of Sales and Marketing for CoreEL.
“With Virage Logic’s highly differentiated IP offering -– including embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and interface IP solutions -– we look forward to being able to provide even greater value to our extensive customer base as we help them address their SoC design challenges.”
Down 2009 likely to lead to growth in 2010 for embedded/RTOS market
DUBLIN, IRELAND: Research and Markets has announced the addition of the "Embedded/Real-time and Mobile Application Operating Systems" report to their offering.
The global recession has, and will continue to, negatively impact the market for embedded/real-time and mobile application operating systems.
Although limited growth is expected within certain vertical markets in 2009, VDC expects the overall market growth to rebound materially in 2010. The changing economic climate has led to a more cautious development approach:
In the recent past, engineering teams would have made more of the software purchasing decisions with minimal process requirements that were managed inside teams.
Since the middle of last year, the process has become more controlled and involves more formal review and approval from higher-levels of engineering management. OEMs have begun vigorously re-evaluating "build-versus-buy" cost analysis.
* More complexity and functionality/new features in software.
* Sustained time-to-market pressures.
* Increasing management oversight on development budgets.
* Reduced engineering resources.
Software vendors are under increasing pressure to articulate and deliver highly differentiated product offerings as industry consortia accelerate the maturation and value proposition of non-commercial, open source operating systems.
This study covers the worldwide market for embedded/real-time and mobile application operating systems employed in the development of embedded and mobile systems. Specifically, our research efforts focused on the markets for:
Real-time operating systems as well as non real-time operating systems used in embedded applications; and Mobile application operating systems used in embedded applications.
The analysis includes revenue from companies that offer the above operating system types, in cases where operating system and bundled product revenue represents a majority of product sales. Therefore, also included within this analysis is other licensing revenue for operating system suppliers that may be derived from:
* Development tools;
* Middleware;
* Product maintenance and support;
* Professional service fees; and
* Other bundled products and services.
The recently published report indicates that embedded system manufacturers' requirements and end-consumers' expectations continue to drive substantial investment in embedded software and development tools.
The embedded and real-time operating system market, in particular, has faired better than many other sectors of the broader embedded market, with 2008 revenue demonstrating 9 percent growth over 2007. However, even this achievement is qualified with the expectation of the first industry contraction in 2009 since 2002.
"As a whole, the embedded operating system market has been greatly affected by the reduction in unit shipments over the past nine months due to the substantial percentage of market revenues typically derived from production licenses," says Chris Rommel, Analyst with VDC's Embedded Software and Tools Practice. "However, the magnitude of the recession's impact has been tempered within the embedded and real-time segment due to the growing demands for software-driven functionality coupled with mounting device safety and security considerations and new device requirements."
Although the recession has and is expected to continue to negatively impact the market for embedded and real-time operating systems in 2009, certain vertical markets have been less affected in the short term while others hold the potential to rebound significantly in 2010.
For example, innovation within the medical device industry will drive growth as cart-mounted devices consolidate sensing and computing components into smaller, mobile form factors and device software is placed under greater regulatory scrutiny. By contrast, the retail automation industry market is expected to demonstrate the largest percent decrease from 2008 to 2009 as retail stores combat falling revenues by limiting capital expenditures on new kiosks and POS equipment.
However, we expect the retail segment to rebound significantly after showing modest growth in 2010 to grow in excess of 20 percent in 2011 as these companies begin to parlay increased cash flow into investments in enhancing efficiencies and consumer experiences.
We expect market participants who, in spite of the current economic climate, remain focused on targeted product development for and marketing to these and other key vertical markets will improve their ability to emerge from this downturn with greater revenue growth and market share.
The global recession has, and will continue to, negatively impact the market for embedded/real-time and mobile application operating systems.
Although limited growth is expected within certain vertical markets in 2009, VDC expects the overall market growth to rebound materially in 2010. The changing economic climate has led to a more cautious development approach:
In the recent past, engineering teams would have made more of the software purchasing decisions with minimal process requirements that were managed inside teams.
Since the middle of last year, the process has become more controlled and involves more formal review and approval from higher-levels of engineering management. OEMs have begun vigorously re-evaluating "build-versus-buy" cost analysis.
* More complexity and functionality/new features in software.
* Sustained time-to-market pressures.
* Increasing management oversight on development budgets.
* Reduced engineering resources.
Software vendors are under increasing pressure to articulate and deliver highly differentiated product offerings as industry consortia accelerate the maturation and value proposition of non-commercial, open source operating systems.
This study covers the worldwide market for embedded/real-time and mobile application operating systems employed in the development of embedded and mobile systems. Specifically, our research efforts focused on the markets for:
Real-time operating systems as well as non real-time operating systems used in embedded applications; and Mobile application operating systems used in embedded applications.
The analysis includes revenue from companies that offer the above operating system types, in cases where operating system and bundled product revenue represents a majority of product sales. Therefore, also included within this analysis is other licensing revenue for operating system suppliers that may be derived from:
* Development tools;
* Middleware;
* Product maintenance and support;
* Professional service fees; and
* Other bundled products and services.
The recently published report indicates that embedded system manufacturers' requirements and end-consumers' expectations continue to drive substantial investment in embedded software and development tools.
The embedded and real-time operating system market, in particular, has faired better than many other sectors of the broader embedded market, with 2008 revenue demonstrating 9 percent growth over 2007. However, even this achievement is qualified with the expectation of the first industry contraction in 2009 since 2002.
"As a whole, the embedded operating system market has been greatly affected by the reduction in unit shipments over the past nine months due to the substantial percentage of market revenues typically derived from production licenses," says Chris Rommel, Analyst with VDC's Embedded Software and Tools Practice. "However, the magnitude of the recession's impact has been tempered within the embedded and real-time segment due to the growing demands for software-driven functionality coupled with mounting device safety and security considerations and new device requirements."
Although the recession has and is expected to continue to negatively impact the market for embedded and real-time operating systems in 2009, certain vertical markets have been less affected in the short term while others hold the potential to rebound significantly in 2010.
For example, innovation within the medical device industry will drive growth as cart-mounted devices consolidate sensing and computing components into smaller, mobile form factors and device software is placed under greater regulatory scrutiny. By contrast, the retail automation industry market is expected to demonstrate the largest percent decrease from 2008 to 2009 as retail stores combat falling revenues by limiting capital expenditures on new kiosks and POS equipment.
However, we expect the retail segment to rebound significantly after showing modest growth in 2010 to grow in excess of 20 percent in 2011 as these companies begin to parlay increased cash flow into investments in enhancing efficiencies and consumer experiences.
We expect market participants who, in spite of the current economic climate, remain focused on targeted product development for and marketing to these and other key vertical markets will improve their ability to emerge from this downturn with greater revenue growth and market share.
An assessment of 3D IC technology
DUBLIN, IRELAND: Research and Markets has announced the addition of Frost & Sullivan's new report "3D IC Technology - An Assessment" to its offering.
This Frost & Sullivan research service titled 3D IC Technology - An Assessment, provides an insight into the technology development scenario of three-dimensional integrated circuit (3D IC) technologies.
This research service also provides a detailed review of the key developmental efforts around the globe, funding scenario, patent analysis, and insights into the key growth patterns that mark the evolution of 3D IC technologies in the industrial space. In this research, Frost & Sullivan's expert analysts thoroughly examine the following technologies: 3D IC, 3D packaging, system in package, and silicon on insulator (SOI) technologies.
'Z' dimension of semiconductor growth impacts advances in image sensor and memory market
There are several development initiatives involving form factor of IC technology, with the much spoken-about difficulty of progressing along the Moore's curve. 3D IC technology assures higher levels of miniaturization and integration, focuses on portraying advances in interconnect technologies, and a reduction of interconnect delays.
3D IC technologies guarantee a significant increase in functionality and performance of components by a heterogeneous integration of materials, devices, and signals. "The adoption of 3D ICs integration technology in different applications is likely to be driven by its capability to reduce process cost, enhance interconnect density, and offer smaller form factors," notes the analyst of this research.
"Although through silicon vias (TSV) has categorically evolved to be a highly competent solution for performance when gauged with conventional interconnect technologies, the industry is still in the process of establishing it as a commercially viable solution for dominant penetration in diverse application sectors."
Currently, the industry is in a position to leverage the capabilities of 3D IC solutions in the image sensors market. Memory stacking is next in line with image sensors in terms of adoption of 3D IC technologies.
At the bottom rung, 3D IC solutions will find opportunities in applications that involve homogeneous integration, while scientists are working toward a technology for applications that need heterogeneous integration of wafers.
As the entire 3D IC technology is focusing on wafer stacking, development efforts around the globe are striving to resolve challenges associated with the silicon on insulator (SOI) domain. The industry is also determined to establish an appropriate performance guideline to enable it to choose between the 'via first' and the 'via last' approaches.
The ability to handle thin wafer, proper bonding technologies for heterogeneous bonding, along with reducing the costs associated with the TSV process are some other critical issues that need to be addressed. "Despite widespread industrial efforts in the 3D IC domain, fundamental technology challenges continue to exist," notes the analyst. "However, the technology space is collaboratively striving to resolve them."
The need of the hour is to establish clear performance metrics for all the evolving processes. For instance, in the case of TSV, the industry has explored aspects, such as the cost of operation (COO) of the process, but lacks a proper standard to gauge the performance of a specific process established by a development group.
This will help participants know the real capabilities of their offering on a global platform. "The next decade of 3D IC evolution will significantly rely on the industry's capability to develop a performance standard for the various segments of 3D IC domain, that are currently being explored," concludes the analyst.
This Frost & Sullivan research service titled 3D IC Technology - An Assessment, provides an insight into the technology development scenario of three-dimensional integrated circuit (3D IC) technologies.
This research service also provides a detailed review of the key developmental efforts around the globe, funding scenario, patent analysis, and insights into the key growth patterns that mark the evolution of 3D IC technologies in the industrial space. In this research, Frost & Sullivan's expert analysts thoroughly examine the following technologies: 3D IC, 3D packaging, system in package, and silicon on insulator (SOI) technologies.
'Z' dimension of semiconductor growth impacts advances in image sensor and memory market
There are several development initiatives involving form factor of IC technology, with the much spoken-about difficulty of progressing along the Moore's curve. 3D IC technology assures higher levels of miniaturization and integration, focuses on portraying advances in interconnect technologies, and a reduction of interconnect delays.
3D IC technologies guarantee a significant increase in functionality and performance of components by a heterogeneous integration of materials, devices, and signals. "The adoption of 3D ICs integration technology in different applications is likely to be driven by its capability to reduce process cost, enhance interconnect density, and offer smaller form factors," notes the analyst of this research.
"Although through silicon vias (TSV) has categorically evolved to be a highly competent solution for performance when gauged with conventional interconnect technologies, the industry is still in the process of establishing it as a commercially viable solution for dominant penetration in diverse application sectors."
Currently, the industry is in a position to leverage the capabilities of 3D IC solutions in the image sensors market. Memory stacking is next in line with image sensors in terms of adoption of 3D IC technologies.
At the bottom rung, 3D IC solutions will find opportunities in applications that involve homogeneous integration, while scientists are working toward a technology for applications that need heterogeneous integration of wafers.
As the entire 3D IC technology is focusing on wafer stacking, development efforts around the globe are striving to resolve challenges associated with the silicon on insulator (SOI) domain. The industry is also determined to establish an appropriate performance guideline to enable it to choose between the 'via first' and the 'via last' approaches.
The ability to handle thin wafer, proper bonding technologies for heterogeneous bonding, along with reducing the costs associated with the TSV process are some other critical issues that need to be addressed. "Despite widespread industrial efforts in the 3D IC domain, fundamental technology challenges continue to exist," notes the analyst. "However, the technology space is collaboratively striving to resolve them."
The need of the hour is to establish clear performance metrics for all the evolving processes. For instance, in the case of TSV, the industry has explored aspects, such as the cost of operation (COO) of the process, but lacks a proper standard to gauge the performance of a specific process established by a development group.
This will help participants know the real capabilities of their offering on a global platform. "The next decade of 3D IC evolution will significantly rely on the industry's capability to develop a performance standard for the various segments of 3D IC domain, that are currently being explored," concludes the analyst.
Peregrine, MagnaChip complete final qualification on UltraCMOS tech transfer
SAN DIEGO, USA & SEOUL, KOREA: Peregrine Semiconductor Corp., a leading supplier of high-performance RF CMOS and mixed-signal communications ICs, and MagnaChip Semiconductor Ltd, a leading Asia-based designer and manufacturer of analog and mixed-signal semiconductor products for high volume consumer applications, have completed the final qualification phase in the process technology transfer of Peregrine’s UltraCMOS SOS (Silicon-On-Sapphire) technology to MagnaChip’s Cheongju wafer manufacturing facility.
Peregrine and MagnaChip began the final qualification phase of the technology transfer in July 2008 and released it to production 8 weeks ago. The 10-month qualification cycle of UltraCMOS technology is exceptionally short due to its standard CMOS foundation.
“We always understood that the value of UltraCMOS to the RF industry would be its unique ability to manufacture products with the highest RF performance possible, and ensure swift portability from fab to fab because of its industry-standard CMOS foundation,” stated Jim Cable, CEO of Peregrine Semiconductor Corp.
“With MagnaChip as a fully qualified and deployed manufacturing resource, our customers continue to be assured of the supply and availability of Peregrine’s products and technology,” he concluded.
The two teams worked diligently to ensure a smooth final qualification, including the completion of a 500 hour reliability test which delivered zero failures. “The initial production lot has been processed through the fab in record time and is used for customer samples,” stated Chandra Kantamneni, Vice President of Foundry Operations at Peregrine Semiconductor.
“Customer qualification audits are underway for MagnaChip’s Cheongju facility and are eagerly anticipating the first deliveries from this additional source,” he added.
Channy Lee, Executive Vice President and General Manager of MagnaChip’s Semiconductor Manufacturing Services, commented: “MagnaChip’s manufacturing services are targeted to customers who require differentiated, specialty analog and mixed-signal process technologies serving high-growth markets. With its revolutionary UltraCMOS SOS technology and high-performance RFIC products, Peregrine exemplifies this type of customer.
"MagnaChip’s reliable manufacturing expertise combined with our customers’ design capabilities will continuously allow us to provide robust and cost-competitive manufacturing solutions to our customers.”
UltraCMOS technology
UltraCMOS mixed-signal process technology is a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate.
This technology provides high yields, competitive costs and delivers significant performance advantages over competing processes such as GaAs, SiGe BiCMOS and bulk silicon CMOS in applications where RF performance, low power and high levels of integration are paramount.
Peregrine and MagnaChip began the final qualification phase of the technology transfer in July 2008 and released it to production 8 weeks ago. The 10-month qualification cycle of UltraCMOS technology is exceptionally short due to its standard CMOS foundation.
“We always understood that the value of UltraCMOS to the RF industry would be its unique ability to manufacture products with the highest RF performance possible, and ensure swift portability from fab to fab because of its industry-standard CMOS foundation,” stated Jim Cable, CEO of Peregrine Semiconductor Corp.
“With MagnaChip as a fully qualified and deployed manufacturing resource, our customers continue to be assured of the supply and availability of Peregrine’s products and technology,” he concluded.
The two teams worked diligently to ensure a smooth final qualification, including the completion of a 500 hour reliability test which delivered zero failures. “The initial production lot has been processed through the fab in record time and is used for customer samples,” stated Chandra Kantamneni, Vice President of Foundry Operations at Peregrine Semiconductor.
“Customer qualification audits are underway for MagnaChip’s Cheongju facility and are eagerly anticipating the first deliveries from this additional source,” he added.
Channy Lee, Executive Vice President and General Manager of MagnaChip’s Semiconductor Manufacturing Services, commented: “MagnaChip’s manufacturing services are targeted to customers who require differentiated, specialty analog and mixed-signal process technologies serving high-growth markets. With its revolutionary UltraCMOS SOS technology and high-performance RFIC products, Peregrine exemplifies this type of customer.
"MagnaChip’s reliable manufacturing expertise combined with our customers’ design capabilities will continuously allow us to provide robust and cost-competitive manufacturing solutions to our customers.”
UltraCMOS technology
UltraCMOS mixed-signal process technology is a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate.
This technology provides high yields, competitive costs and delivers significant performance advantages over competing processes such as GaAs, SiGe BiCMOS and bulk silicon CMOS in applications where RF performance, low power and high levels of integration are paramount.
Carl Zeiss launches next-gen analytical electron microscope
OBERKOCHEN, GERMANY: Carl Zeiss announces a series of launches covering a range of product and application innovations. The start of this series is marked by the next-generation analytical field emission scanning electron microscope –- the MERLIN.
This instrument combines the up to now contradictory requirements of ultra-high resolution imaging and analytical capabilities. “Customers have a need for more than just high resolution images of their samples”, Dr. Dirk Stenkamp, Member of the Board at Carl Zeiss SMT explains. “With unique analytical capabilities our instruments provide maximum information with maximum insight”.
MERLIN -- analysis and high resolution in one
The MERLIN FE-SEM overcomes the conflict between image resolution and analytical capability. The core of MERLIN is the enhanced GEMINI II column which, with its double condenser system, achieves an image resolution of 0.8 nanometers.
A sample current of up to 300 nanoamperes is available for analytical purposes such as energy and wavelength dispersive X-ray spectroscopy (EDS and WDS), diffraction analysis of backscattered electrons (EBSD) or the generation of cathodoluminescence.
The system supports the user with a wide range of detailed solutions for tasks that could not be adequately performed in the past. The foundation for this achievement has been laid by the Carl Zeiss “Complete Detection System”.
This consists of the in-lens SE detector for surface imaging, the in-lens EsB detector for material contrast and the AsB detector for widely dispersed backscattered electrons. The latter contain specific information on the crystal orientation of the sample.
The unique charge compensation system of MERLIN also allows the high-resolution imaging of non-conductive samples. Electrons which accumulate on the surface of the sample are swept away by a fine jet of nitrogen. In doing so, the complete detection system of MERLIN can be used.
An additional feature of the system for charge compensation is a channel for pure oxygen enabling in-situ sample cleaning. Within the vacuum chamber frequently occurring carbon deposits are removed from the sample surface, thus producing a significantly crisper and contrasty image. Both options allow the user to concentrate on the imaging and analysis of the sample instead of investing time and money in sample preparation.
MERLIN’s new electronic system permits a flexible instrument configuration. Additional detectors can be retrofitted quickly, allowing the user to adapt the system to growing requirements. In addition, this flexibility makes the investment more future-proof and enables the user to benefit over the long term from ongoing detector development.
“The new MERLIN, as well as the just recently introduced AURIGA CrossBeam workstation perfectly embody what our products stand for: Maximum Information – Maximum Insight”, Stenkamp points out. “And – the market can expect much more in the coming weeks until M&M show and the European Microscopy Conference in Graz, Austria, end of August.”
This instrument combines the up to now contradictory requirements of ultra-high resolution imaging and analytical capabilities. “Customers have a need for more than just high resolution images of their samples”, Dr. Dirk Stenkamp, Member of the Board at Carl Zeiss SMT explains. “With unique analytical capabilities our instruments provide maximum information with maximum insight”.MERLIN -- analysis and high resolution in one
The MERLIN FE-SEM overcomes the conflict between image resolution and analytical capability. The core of MERLIN is the enhanced GEMINI II column which, with its double condenser system, achieves an image resolution of 0.8 nanometers.
A sample current of up to 300 nanoamperes is available for analytical purposes such as energy and wavelength dispersive X-ray spectroscopy (EDS and WDS), diffraction analysis of backscattered electrons (EBSD) or the generation of cathodoluminescence.
The system supports the user with a wide range of detailed solutions for tasks that could not be adequately performed in the past. The foundation for this achievement has been laid by the Carl Zeiss “Complete Detection System”.
This consists of the in-lens SE detector for surface imaging, the in-lens EsB detector for material contrast and the AsB detector for widely dispersed backscattered electrons. The latter contain specific information on the crystal orientation of the sample.
The unique charge compensation system of MERLIN also allows the high-resolution imaging of non-conductive samples. Electrons which accumulate on the surface of the sample are swept away by a fine jet of nitrogen. In doing so, the complete detection system of MERLIN can be used.
An additional feature of the system for charge compensation is a channel for pure oxygen enabling in-situ sample cleaning. Within the vacuum chamber frequently occurring carbon deposits are removed from the sample surface, thus producing a significantly crisper and contrasty image. Both options allow the user to concentrate on the imaging and analysis of the sample instead of investing time and money in sample preparation.
MERLIN’s new electronic system permits a flexible instrument configuration. Additional detectors can be retrofitted quickly, allowing the user to adapt the system to growing requirements. In addition, this flexibility makes the investment more future-proof and enables the user to benefit over the long term from ongoing detector development.
“The new MERLIN, as well as the just recently introduced AURIGA CrossBeam workstation perfectly embody what our products stand for: Maximum Information – Maximum Insight”, Stenkamp points out. “And – the market can expect much more in the coming weeks until M&M show and the European Microscopy Conference in Graz, Austria, end of August.”
Verigy's SmartRA redundancy analysis option for V6000 WS
CUPERTINO, USA: Verigy, a premier semiconductor test company, has introduced SmartRA (Scalable Memory Redundancy Technology), a memory redundancy analysis (RA) option for its V6000 WS test system.
SmartRA provides a scalable, flexible, cost-effective solution that allows manufacturers to meet the expanding fail storage and performance requirements of redundancy analysis for DRAM.
SmartRA will be showcased at the SEMICON West trade show in Verigy’s Booth #921, South Hall, July 14-16, 2009 at the Moscone Convention Center in San Francisco.
Verigy’s V6000 WS, introduced in November 2008, is the industry’s first scalable, high-volume wafer sort test system for both Flash and DRAM applications. With SmartRA, V6000 WS users can easily add redundancy analysis capabilities for increased throughput and yield.
As DRAM device densities continue to increase, so do the challenges of today's wafer sort testing, requiring greater test parallelism, higher test frequencies and increased levels of complexity in device redundancy.
These factors result in unprecedented volumes of data during redundancy analysis. Consequently, the storage and performance required to capture fail data and effectively complete redundancy analysis are also reaching new levels.
Verigy designed SmartRA to meet these requirements and because the solution utilizes high-performance blade servers, manufacturers can add processing power for redundancy analysis as they need it, without impacting the test cell footprint.
SmartRA is based on an open software architecture which makes it possible for customers to use Verigy-provided algorithms or develop their own for faster time to market and lower cost-of-test.
Verigy designed SmartRA to meet these requirements and because the solution utilizes high-performance blade servers, manufacturers can add processing power for redundancy analysis as they need it, without impacting the test cell footprint.
SmartRA is based on an open software architecture which makes it possible for customers to use Verigy-provided algorithms or develop their own for faster time to market and lower cost-of-test.
SmartRA provides a scalable, flexible, cost-effective solution that allows manufacturers to meet the expanding fail storage and performance requirements of redundancy analysis for DRAM.
SmartRA will be showcased at the SEMICON West trade show in Verigy’s Booth #921, South Hall, July 14-16, 2009 at the Moscone Convention Center in San Francisco.
Verigy’s V6000 WS, introduced in November 2008, is the industry’s first scalable, high-volume wafer sort test system for both Flash and DRAM applications. With SmartRA, V6000 WS users can easily add redundancy analysis capabilities for increased throughput and yield.
As DRAM device densities continue to increase, so do the challenges of today's wafer sort testing, requiring greater test parallelism, higher test frequencies and increased levels of complexity in device redundancy.
These factors result in unprecedented volumes of data during redundancy analysis. Consequently, the storage and performance required to capture fail data and effectively complete redundancy analysis are also reaching new levels.
Verigy designed SmartRA to meet these requirements and because the solution utilizes high-performance blade servers, manufacturers can add processing power for redundancy analysis as they need it, without impacting the test cell footprint.
SmartRA is based on an open software architecture which makes it possible for customers to use Verigy-provided algorithms or develop their own for faster time to market and lower cost-of-test.
Verigy designed SmartRA to meet these requirements and because the solution utilizes high-performance blade servers, manufacturers can add processing power for redundancy analysis as they need it, without impacting the test cell footprint.
SmartRA is based on an open software architecture which makes it possible for customers to use Verigy-provided algorithms or develop their own for faster time to market and lower cost-of-test.
Innovasic's pin-compatible 80C186XL and 80C188XL embedded processors
ALBUQUERQUE, USA: Innovasic Semiconductor, a leader in extended life semiconductor solutions, announced engineering samples are shipping for the IA186XL and IA188XL.
The IA186XL and IA188XL are form, fit, and function compatible with the original Intel 80C186XL and 80C188XL 16-bit high-integration embedded processors, and also serve as replacements for the Intel base 80C186 and 80C188 devices. The IA186XL and IA188XL are the latest additions to Innovasic’s growing 18x product family.
The Innovasic version supports internal 20-25 MHz operation and is industrial temperature grade. The Innovasic processors have the same set of peripherals as the Intel devices, including the standard numeric interface, interrupt control unit, chip-select unit/Ready Generation Logic, DRAM refresh control unit, power management unit, three 16-bit timer/counters, and two independent DMA channels.
The IA186XL and IA188XL are available in 68-Pin PLCC, 80-Pin PQFP, and 80-Pin LQFP RoHS compliant packages.
Engineering samples may be ordered on the Innovasic website.
The IA186XL and IA188XL are form, fit, and function compatible with the original Intel 80C186XL and 80C188XL 16-bit high-integration embedded processors, and also serve as replacements for the Intel base 80C186 and 80C188 devices. The IA186XL and IA188XL are the latest additions to Innovasic’s growing 18x product family.The Innovasic version supports internal 20-25 MHz operation and is industrial temperature grade. The Innovasic processors have the same set of peripherals as the Intel devices, including the standard numeric interface, interrupt control unit, chip-select unit/Ready Generation Logic, DRAM refresh control unit, power management unit, three 16-bit timer/counters, and two independent DMA channels.
The IA186XL and IA188XL are available in 68-Pin PLCC, 80-Pin PQFP, and 80-Pin LQFP RoHS compliant packages.
Engineering samples may be ordered on the Innovasic website.
DDR3 July contract price likely to rise 5~10 percent
TAIPEI, TAIWAN: The June contract price did not fluctuate since some contract deals between PC OEMs and DRAM vendors are conducted either in monthly basis or quarterly basis. DRAMeXchange believes that DDR3 contract price in July will increase 5 percent~10 percent due to the aggressive CULV promotion and new contract deal negotiation in July.
As for spot market, given the stable range between $1.5~$1.7 of DDR3 1Gb chip with 50 percent premium compared to DDR2 1Gb chip, DDR2 1Gb chip price has dropped to $1 from $1.34 in May, says DRAMeXchange.
From the supply side perspective, DRAM vendors adopted the “Capacity Cut” strategy through the difficult period in 2H’08 given the frozen demand and global financial crisis. Qimonda was filed bankruptcy early this year, while ProMOS maintained the minimum operation.
With the improved economy, DRAM vendors gradually enhance production. DDR3 wafer-in portion is expected to be up to 30 percent in Q4’09 from 15 percent in Q1’09, while Korean and Japanese vendors demonstrate the great ambition on the DDR3 migration.
Nanya and Inotera are the only capable Taiwanese vendors that can dedicate to DDR3 production. However, the DDR3 portion of Nanya and Inotera is below 10 percent, while the remaining 90 percent is occupied by Korean and Japanese vendors (see Fig. 1).
DRAM vendors were suffering from the big financial trough in the downturn economy crisis that this circumstance resulted in the obvious CAPEX gap especially in DDR3 migration. This situation is way different from what DRAM vendors devoted CAPEX in 70nm and 65nm technology. As for Korean vendors, they do aggressively conduct not only DDR3 migration, but 50nm technology adoption as well.
It is expected that at least 70 percent DDR3 chips will be produced with 50m technology. 65nm remains current mainstream technology for Japanese vendors that they do contend competitiveness if the total chip amount can be increased via “Die Shrink” process.
Although Qimonda’s 70nm technology is still adopted to produce DDR3, Micron’s 68nm and 50nm technology will be mainly applied in 2H’09. This technology migration will give Nanya and Inotera some credit to compete with Korean/Japanese vendors. Meanwhile, Powerchip and Rexchip are both qualified for mess production, according to DRAMeXchange (see Fig. 2).
As for spot market, given the stable range between $1.5~$1.7 of DDR3 1Gb chip with 50 percent premium compared to DDR2 1Gb chip, DDR2 1Gb chip price has dropped to $1 from $1.34 in May, says DRAMeXchange.
From the supply side perspective, DRAM vendors adopted the “Capacity Cut” strategy through the difficult period in 2H’08 given the frozen demand and global financial crisis. Qimonda was filed bankruptcy early this year, while ProMOS maintained the minimum operation.
With the improved economy, DRAM vendors gradually enhance production. DDR3 wafer-in portion is expected to be up to 30 percent in Q4’09 from 15 percent in Q1’09, while Korean and Japanese vendors demonstrate the great ambition on the DDR3 migration.
Nanya and Inotera are the only capable Taiwanese vendors that can dedicate to DDR3 production. However, the DDR3 portion of Nanya and Inotera is below 10 percent, while the remaining 90 percent is occupied by Korean and Japanese vendors (see Fig. 1).
DRAM vendors were suffering from the big financial trough in the downturn economy crisis that this circumstance resulted in the obvious CAPEX gap especially in DDR3 migration. This situation is way different from what DRAM vendors devoted CAPEX in 70nm and 65nm technology. As for Korean vendors, they do aggressively conduct not only DDR3 migration, but 50nm technology adoption as well.
It is expected that at least 70 percent DDR3 chips will be produced with 50m technology. 65nm remains current mainstream technology for Japanese vendors that they do contend competitiveness if the total chip amount can be increased via “Die Shrink” process.
Although Qimonda’s 70nm technology is still adopted to produce DDR3, Micron’s 68nm and 50nm technology will be mainly applied in 2H’09. This technology migration will give Nanya and Inotera some credit to compete with Korean/Japanese vendors. Meanwhile, Powerchip and Rexchip are both qualified for mess production, according to DRAMeXchange (see Fig. 2).
Wednesday, July 1, 2009
Hitachi achieves 40pc reduction in PCB place-and-route design time with Cadence GRE
SAN JOSE, USA: Cadence Design Systems Inc. announced that the Cadence Global Route Environment (GRE) technology for Cadence Allegro PCB design enabled Hitachi Ltd. to successfully reduce PCB place-and-route design time by 40 percent for a high-speed communication product.
Hitachi applied the GRE place-and-route design methodology to its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where no automation was previously available.
The time-saving results were reported by Hitachi Communication Technologies, Ltd., the communication products division of Hitachi Group, as part of a companywide initiative at Hitachi to enhance design efficiency and reduce design-cycle time.
“High-speed PCBs require significant enhancements in performance, and gigahertz-level signals are becoming common,” said Toru Hiyama, general manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi.
“Hitachi is always aiming at high-performance, high-quality products, and in order to complete the design in the shortest cycle time possible while maintaining high quality, it was critical for us to solve the bottleneck of place-and-route for PCBs. By using Cadence GRE technology, we can solve the routing bottleneck as well as enhance the reliability of the design.”
The Cadence GRE technology is the next-generation interconnect planning and routing technology for PCB, and establishes a new PCB design paradigm. The GRE technology provides users with automation for various stages of interconnect planning and routing where no automation has been available. At the beginning of the process it allows users to plan the routing strategy at a high-level through Interconnect Flow Designer.
Through the Interconnect Feasibility capability it checks and provides feedback on available space for each of the flows, allowing users to modify their routing strategy. In the middle of the planning process, it determines the overall routing feasibility, including the routing paths, net topologies and assigned electric constraints.
In the final planning phase, the GRE technology performs feasibility routing against the pre-determined routing flow, and then automatically completes routing. This approach becomes very effective for memory interfaces such as DDR2, DDR3, and serial interfaces such as PCI Express and PCI Express Gen II with their stringent high-speed design constraints.
At Hitachi, automatic routing had not previously been available to route signals with high-speed constraints. The GRE technology dramatically improves the quality of PCB designs by enabling users to concurrently work on the placement and the exploration of the routing strategies and paths.
With GRE, Hitachi was able to effectively manage PCB designs with various tradeoffs. Hitachi expects further reduction of design time as the GRE performance and features are updated and further enhanced.
In March 2007, Hitachi and Cadence jointly announced that Hitachi had standardized on Cadence EDA products in order to enhance design efficiency and reduce the design-cycle time for Hitachi's hardware products as part of its focus on the company's manufacturing capability.
“Cadence GRE technology is the next generation of PCB interconnect planning and routing technology. It offers automation for designs with high-speed interfaces such as DDR2, SATA, and PCI Express,” said AJ Incorvaia, vice president of research & development, Allegro - R&D Development at Cadence.
“In order to design today’s PCBs with high-speed constraints while maintaining quality levels like those of Hitachi, it is imperative to make route strategy trade-offs at early stages of design as well as have a unified and global methodology for routing. By combining their high-level requirements PCB design with GRE technology, Hitachi is able to significantly shorten their overall PCB design cycle. This success will become a standard reference for a new design methodology for high-speed PCBs.”
In addition to the full-constraints routing capability, Hitachi said the GRE technology will be effective for many other PCB design challenges, such as engineering changes and routing estimation. Hitachi plans to deploy and promote the GRE technology as a standard solution throughout the design environment.
Hitachi applied the GRE place-and-route design methodology to its PCB place-and-route from interconnect planning to complete routing, with full constraints for high-speed digital signals where no automation was previously available.
The time-saving results were reported by Hitachi Communication Technologies, Ltd., the communication products division of Hitachi Group, as part of a companywide initiative at Hitachi to enhance design efficiency and reduce design-cycle time.
“High-speed PCBs require significant enhancements in performance, and gigahertz-level signals are becoming common,” said Toru Hiyama, general manager, MONOZUKURI Innovation Operation, Hardware MONOZUKURI Division at Hitachi.
“Hitachi is always aiming at high-performance, high-quality products, and in order to complete the design in the shortest cycle time possible while maintaining high quality, it was critical for us to solve the bottleneck of place-and-route for PCBs. By using Cadence GRE technology, we can solve the routing bottleneck as well as enhance the reliability of the design.”
The Cadence GRE technology is the next-generation interconnect planning and routing technology for PCB, and establishes a new PCB design paradigm. The GRE technology provides users with automation for various stages of interconnect planning and routing where no automation has been available. At the beginning of the process it allows users to plan the routing strategy at a high-level through Interconnect Flow Designer.
Through the Interconnect Feasibility capability it checks and provides feedback on available space for each of the flows, allowing users to modify their routing strategy. In the middle of the planning process, it determines the overall routing feasibility, including the routing paths, net topologies and assigned electric constraints.
In the final planning phase, the GRE technology performs feasibility routing against the pre-determined routing flow, and then automatically completes routing. This approach becomes very effective for memory interfaces such as DDR2, DDR3, and serial interfaces such as PCI Express and PCI Express Gen II with their stringent high-speed design constraints.
At Hitachi, automatic routing had not previously been available to route signals with high-speed constraints. The GRE technology dramatically improves the quality of PCB designs by enabling users to concurrently work on the placement and the exploration of the routing strategies and paths.
With GRE, Hitachi was able to effectively manage PCB designs with various tradeoffs. Hitachi expects further reduction of design time as the GRE performance and features are updated and further enhanced.
In March 2007, Hitachi and Cadence jointly announced that Hitachi had standardized on Cadence EDA products in order to enhance design efficiency and reduce the design-cycle time for Hitachi's hardware products as part of its focus on the company's manufacturing capability.
“Cadence GRE technology is the next generation of PCB interconnect planning and routing technology. It offers automation for designs with high-speed interfaces such as DDR2, SATA, and PCI Express,” said AJ Incorvaia, vice president of research & development, Allegro - R&D Development at Cadence.
“In order to design today’s PCBs with high-speed constraints while maintaining quality levels like those of Hitachi, it is imperative to make route strategy trade-offs at early stages of design as well as have a unified and global methodology for routing. By combining their high-level requirements PCB design with GRE technology, Hitachi is able to significantly shorten their overall PCB design cycle. This success will become a standard reference for a new design methodology for high-speed PCBs.”
In addition to the full-constraints routing capability, Hitachi said the GRE technology will be effective for many other PCB design challenges, such as engineering changes and routing estimation. Hitachi plans to deploy and promote the GRE technology as a standard solution throughout the design environment.
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