CUPERTINO, USA: Chip Path Design Systems announced its formation from Parallel Engines Corp. Chip Path is focusing on a new set of Semiconductor-IP based Architecture tools for ASIC, FPGA and ASSP design.
The company has developed a new “One Architecture” specification system that allows a single architecture to be mapped onto multiple implementation platforms. Company labels this approach “Semantic-IC Design,” following in Web 3.0 nomenclature.
Electronic Design Automation (EDA) pioneer George Janac has been appointed to head the effort as CEO and Chairman. “In today’s market there is an abundance of chip choices to use in products,” said Janac, “but the ability to decide if volumes and costs warrant a new ASIC, utilize an existing ASSP, or quick time to market FPGA remains elusive.”
Chip Path has aggregated extensive databases of high level models for Semiconductor-IP, IC-Technology, and FPGA (Field Programmable Gate Array) devices into a specification for very rapid/accurate compilation and Total Cost of Ownership analysis. Parts costs today are only a small fraction of the total picture. There is a huge need to know if an existing device can meet product goals or if a lengthy deep-submicron design process is warranted.
“What I am the most excited about with ChipPath is the ability to bring Design Planning (Floorplanning) into the Architectural and Semiconductor-IP age,” said CEO George Janac. “We really can get to the point that ICs are Cut-and-Paste assembled from I/O Channels, Subsystems, and Networks-on-Chip.”
Company founders have prior experience in both Semiconductor-IP and Design Planning, having founded High Level Design Systems, Chip Estimate, InTime Software, and funded Hier Design, all related to this area. Chip Path has disclosed that it plans to offer both Web-based tools as well as a classic Linux downloadable tool model.
The company plans to announce and release products in rapid succession over the next year.