Thursday, July 2, 2009

Verigy's SmartRA redundancy analysis option for V6000 WS

CUPERTINO, USA: Verigy, a premier semiconductor test company, has introduced SmartRA (Scalable Memory Redundancy Technology), a memory redundancy analysis (RA) option for its V6000 WS test system.

SmartRA provides a scalable, flexible, cost-effective solution that allows manufacturers to meet the expanding fail storage and performance requirements of redundancy analysis for DRAM.

SmartRA will be showcased at the SEMICON West trade show in Verigy’s Booth #921, South Hall, July 14-16, 2009 at the Moscone Convention Center in San Francisco.

Verigy’s V6000 WS, introduced in November 2008, is the industry’s first scalable, high-volume wafer sort test system for both Flash and DRAM applications. With SmartRA, V6000 WS users can easily add redundancy analysis capabilities for increased throughput and yield.

As DRAM device densities continue to increase, so do the challenges of today's wafer sort testing, requiring greater test parallelism, higher test frequencies and increased levels of complexity in device redundancy.

These factors result in unprecedented volumes of data during redundancy analysis. Consequently, the storage and performance required to capture fail data and effectively complete redundancy analysis are also reaching new levels.

Verigy designed SmartRA to meet these requirements and because the solution utilizes high-performance blade servers, manufacturers can add processing power for redundancy analysis as they need it, without impacting the test cell footprint.

SmartRA is based on an open software architecture which makes it possible for customers to use Verigy-provided algorithms or develop their own for faster time to market and lower cost-of-test.

Verigy designed SmartRA to meet these requirements and because the solution utilizes high-performance blade servers, manufacturers can add processing power for redundancy analysis as they need it, without impacting the test cell footprint.

SmartRA is based on an open software architecture which makes it possible for customers to use Verigy-provided algorithms or develop their own for faster time to market and lower cost-of-test.

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