Innovasic's pin-compatible 80C186XL and 80C188XL embedded processors

ALBUQUERQUE, USA: Innovasic Semiconductor, a leader in extended life semiconductor solutions, announced engineering samples are shipping for the IA186XL and IA188XL.

The IA186XL and IA188XL are form, fit, and function compatible with the original Intel 80C186XL and 80C188XL 16-bit high-integration embedded processors, and also serve as replacements for the Intel base 80C186 and 80C188 devices. The IA186XL and IA188XL are the latest additions to Innovasic’s growing 18x product family.

The Innovasic version supports internal 20-25 MHz operation and is industrial temperature grade. The Innovasic processors have the same set of peripherals as the Intel devices, including the standard numeric interface, interrupt control unit, chip-select unit/Ready Generation Logic, DRAM refresh control unit, power management unit, three 16-bit timer/counters, and two independent DMA channels.

The IA186XL and IA188XL are available in 68-Pin PLCC, 80-Pin PQFP, and 80-Pin LQFP RoHS compliant packages.

Engineering samples may be ordered on the Innovasic website.

OCP-IP releases OCP 3.0 specification

BEAVERTON, USA: Open Core Protocol International Partnership (OCP-IP) has released the OCP 3.0 specification for member review. This latest version contains extensions to support cache coherence and more aggressive power management, as well as an additional high-speed consensus profile and other new elements.

Embedded processors commonly used in SoCs often use local caches to improve performance and reduce power by storing frequently referenced storage locations in high bandwidth low latency local memories. Keeping such caches coherent with the external memories that they shadow requires either careful software engineering or costly hardware resources that have been considered too expensive for most SoCs.

However, maintaining coherence in embedded software is becoming very complex so the OCP 3.0 coherence extensions are included to enable hardware-based coherence among the wide variety of heterogeneous CPUs, DSPs, accelerators and streaming input/output devices that characterize advanced SoCs.

The OCP extensions differ from traditional coherence approaches by cleanly separating the primitive operations associated with maintaining coherence from the specific system-level approach for implementing the communication and storage aspects of a coherent system. This extends a key advantage of OCP -– the ability to develop IP cores independently from the system in which they will be used –- into the domain of cache coherent systems.

In particular, the OCP coherence extensions have been validated against both invalidate-based snoopy and directory-based coherence schemes.

As power minimization is important in most electronic systems, designers are increasingly implementing power management protocols on chip. OCP 3.0 defines a new connection protocol that allows the power management hardware to disconnect the OCP interface without losing any transaction so the manager may then independently shut off power.

Consensus profiles provide company engineers with standardized configurations of OCP options for specific system use cases, ensuring interoperability. A third profile (Profile 3) has been added in OCP 3.0. Profile 1 is a simple slave profile. Profile 2 is a high-speed profile, and Profile 3 is an advanced high-speed profile needed for high speed CPUs, high-performance video graphics accelerators and DRAMS. A detailed technical article on consensus profiles is available here.

“OCP-IP believes a standard is only proven through real-world implementations and products,” said Ian Mackintosh president and chairman of OCP-IP. “OCP-IP members, companies with world-class SoC design expertise in their own right, have used OCP in numerous SoC designs and have already shipped many hundreds of million of units. OCP 3.0 utilizes the collective experience of these SoC designers and EDA providers and directly addresses their enhancement recommendations with the new specification.”

Work on OCP 3.0 was executed by members of the OCP-IP Specification Working Group including: MIPS Technologies, Nokia, Sonics Inc, Texas Instruments, Toshiba and other industry leading companies.

Altera Nios II processor gets Wind River Linux support

Wind River recently announced the Wind River Linux support for Altera’s Nios II embedded processor.

Commenting on the Nios II processor adoptiion, Mikeson Wang, Product Marketing Manager, Asia Pacific, Altera Corp., in Hong Kong, highlighted that it has over 20,000 licensees worldwide, and is used by each one of the top 20 OEMs. The Nios II processor happens to be the industry’s #1 soft core CPU, as per Gartner Dataquest. There exists a very vibrant Nios Forum community of over 10,000 users. It is also used by developers in all Altera markets.

Wind River delivers Linux support for the Nios II processor also means that the #1 FPGA processor is now supported by best-in-class embedded Linux. Also, Nios II plus embedded Linux = BOM cost reduction.

It is a compelling alternative to discrete off-the-shelf processors. Wind River customers have access to Altera’s full spectrum of FPGA and HardCopy ASIC solutions as well.

Wang added that the Nios II is popular because of providing design flexibility. Being a custom fit solution, it is also easy to modify hardware at any time.

Why Linux + Nios II
There are several reasons. First, it provides cost reduction through integration. Users can replace the existing CPU with an FPGA running Embedded Linux. Next, it provides protection from processor obsolescence. This in turn, protects the software legacy code, which happens to be a customer's biggest investment.

This combination also allows design flexibility. Besides providing access to open source software, the time to market gets reduced as well.

Highlighting the reasons for the Altera-Wind River partnership, he added that Wind River is the best-in-class Linux partner, with worldwide sales, support, training and service infrastructure. Wind River is also the no. 1 embedded OS supplier for the communications market.

Altera itself has a strong presence in the communications market. Also, the FPGA processor use is a growing trend in embedded applications; and Nios II is leading FPGA soft processor. There is also a significant overlap of Altera and Wind River's customer base, such as Huawei, ZTE, Motorola, Alcatel-Lucent, etc., to name a few.

Deliveables include:
Altera
* Cyclone III FPGA Development Kit (3C120)
- DK-DEV-3C120
* Linux Hardware Reference Design (Quartus II Project)
- Current design: 125 MHz in 3C120
- Nios II performance: 150 – 300 DMIPS *

Wind River
* Wind River Linux Distribution
* Wind River Workbench for Nios II
- Workbench IDE with Nios II Support
- GNU Tool Chain, Board Support Package
* Flash files (HW & SW for 3C120 board)

The Cyclone III FPGA development kit is a complete platform for prototyping embedded systems.

In summary, the Wind River-Altera partnership helps reduce system cost and TTM, and increases system flexibility. Altera and Wind River already share several customers, and hence, this is a win-win partnership. The strategic partnership with Wind River complements Altera's silicon, soft processor and FPGA development, besides, Wind River's industry-leading embedded Linux distribution.

How will this partnership boost FPGA sales? According to Wang: "The current weak demand is due to recession. We see weak demand in every segment. However, we are still outperforming the market."

Although leading-edge FPGAs are scaling to 40nm and beyond, have the tools caught up with these new and complex processes? Wang added that the process does not have any significant impact.