Cadence was kind enough to discuss its Allegro solution with me recently. The solution aims at enhancing the productivity for next-generation PCB designs.
According to Steve Kamin, Group Director, Cadence's Allegro systems division, customers face constraints such as higher frequency, power consumption, pin counts, packages, etc. The PCB designers also face challenges such as decreasing hole sizes, hole diameter, etc.
Features of the Allegro include GUI (graphical user interface) modernization, context sensitive editing paradigm, color and visibility improvements, integration of physical and spacing constraints into the Constraint Manager, and an interactive planning and global routing, respectively.
In a PCB design flow, Cadence has focused on usability and productivity. The Allegro has a modernized GUI. All of the tool bars have been completely refreshed. Cadence has also added foldaway windows.
Cadence has added context-sensitive editing and included an open GL graphics engine that improves the visibility of objects and components on a board. This release can handle all sorts of intricate designs.
It has also addressed the physical and spacing constraints, which has been included that into the Constraint Manager. This is a cockpit, a spreadsheet-based tool, which manages all of the properties. Cadence is selling this solution to OEMs, ODMs, PCB design services companies, etc.
The Allegro solution has an interactive planning and global routing facility. Cadence has also added an entry-level product in the OrCAD PCB Designer Basics. Its GRE is a new, next-generation technology, which has two new elements -- the interactive flow planner and the Global Route Environment.
The GRE cuts to 1-2 iteration of routing. Customers can control the direction of the routes. Fabricators sometimes have had to kill the design as they could not control the routing or it was not possible. Hence, Allegro takes care of this issue. It saves significant time, from 15 months to about three months.
Allegro facilitates an improved design creation and simulation as well. The Allegro System Architect has differential pairs support and improved schematic generation. Other features include physical and spacing constraints in Allegro Design Entry HDL, performance and convergence improvements in Cadence Pspice and Allegro AMS Simulator, etc. Cadence has improved the automatic schematic generator. Also, in the analog simulation product line, it has added the automated convergence capability.
Finally, the company has added Cadence Help across all of its products. This allows cross-linking across all Cadence's tools. Customers can also add their own content. Cadence integrates third-party thermal integration tools into the products.
Showing posts with label PCB services. Show all posts
Showing posts with label PCB services. Show all posts
Monday, May 28, 2007
Sunday, April 1, 2007
Take care of thermal distribution for higher-layer PCBs
This is an extension to an earlier piece on the subject. During my various meetings in Hong Kong, I found Johnny Keung, deputy general manager, Circuitone, as a very good resource for discussing PCB services.
He described that immersion tin was economical, complied with RoHS, could replace immersion gold, and go fine line width. Circuitone offers 4µx4µ line width. As for spacing, it can go down to 3µ spacing.
The board size can be limited by equipment. Circuitone has equipment that handles 24x24inch board sizes. It can also offer 0.003” line width (3µx3µ) for high-density PCBs in large volumes. It offers minimum hole-width of 0.2mm, and plans to offer 0.1mm hole-width by Q4-07. This is indeed significant.
There had been some reports in the trade press regarding some Mainland Chinese PCB fabricators offeing 20- and even 40-layer PCBs.
Keung said there were two benchmarks. One, switching from double-sided to four layers, and two, switching from four layers to six layers.
He pointed out that Circuitone could use technology from six layers up to 20 layers. If it went beyond 20 layers, for example, 22 layers, there may be difficulties with thermal distribution within the board.
As I understand from our discussions, for up to 20 layers or so, heat distribution was on the top layer of the PCB, while distribution across middle layer could be uneven. Layers at the bottom could experience higher heat transfer than those in the middle.
Even PCB pressing is done in two stages: one, increase heat so the bonding sheet started to melt, and two, if temperature kept increasing, the glue was transformed into solid. This was the final curing stage.
Commenting on 40-layer PCBs, Keung commented that those boards at the outer layer would likely start melting, and those at the core layer would be in solidstate. When heat was being transferred into core layer, the evenness of distribution changed. The outer layer would remain in solidstate as well. So, expansion/contraction could get uneven, and registration could be a big challenge.
Fabricators should definitely look into this aspect, before designing higher-layer PCBs. I believe, some research work has been done by PCB makers to develop higher-layer PCBs. We discussed the yield rate earlier. That has to rise.
He described that immersion tin was economical, complied with RoHS, could replace immersion gold, and go fine line width. Circuitone offers 4µx4µ line width. As for spacing, it can go down to 3µ spacing.
The board size can be limited by equipment. Circuitone has equipment that handles 24x24inch board sizes. It can also offer 0.003” line width (3µx3µ) for high-density PCBs in large volumes. It offers minimum hole-width of 0.2mm, and plans to offer 0.1mm hole-width by Q4-07. This is indeed significant.
There had been some reports in the trade press regarding some Mainland Chinese PCB fabricators offeing 20- and even 40-layer PCBs.
Keung said there were two benchmarks. One, switching from double-sided to four layers, and two, switching from four layers to six layers.
He pointed out that Circuitone could use technology from six layers up to 20 layers. If it went beyond 20 layers, for example, 22 layers, there may be difficulties with thermal distribution within the board.
As I understand from our discussions, for up to 20 layers or so, heat distribution was on the top layer of the PCB, while distribution across middle layer could be uneven. Layers at the bottom could experience higher heat transfer than those in the middle.
Even PCB pressing is done in two stages: one, increase heat so the bonding sheet started to melt, and two, if temperature kept increasing, the glue was transformed into solid. This was the final curing stage.
Commenting on 40-layer PCBs, Keung commented that those boards at the outer layer would likely start melting, and those at the core layer would be in solidstate. When heat was being transferred into core layer, the evenness of distribution changed. The outer layer would remain in solidstate as well. So, expansion/contraction could get uneven, and registration could be a big challenge.
Fabricators should definitely look into this aspect, before designing higher-layer PCBs. I believe, some research work has been done by PCB makers to develop higher-layer PCBs. We discussed the yield rate earlier. That has to rise.
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