Mentor Graphics design and verification tools certified for TSMC 16nm FinFET

USA: Mentor Graphics Corp. announced that its Calibre physical verification platform has achieved version 0.1 of design reference manual (DRM) and SPICE model tool certification for TSMC’s 16nm manufacturing process, which incorporates 3D (FinFET) transistors for higher performance.

TSMC has given 0.1 Certification to the Mentor Olympus-SoC place and route system, and the Calibre physical verification platform. The Mentor 16nm platforms are now available to support customers with their early 16nm FinFET design efforts.

The Mentor Olympus-SoC place and route system for 16nm FinFET enables efficient double patterning (DP) and timing closure with comprehensive support for new design rule checks and multi-patterning rules, fin grid alignment for standard cells and macros during placement, and Vt min-area rule and implant layer support during placement.

The Calibre nmPlatform product for 16nm FinFET supports advanced design rule definition and litho hotspot pre-filtering. In addition, the Calibre SmartFill facility was enhanced to support the TSMC-specified filling requirements for FinFET transistors, including support for density constraints and multilayer structures needed for FinFET layers. The SmartFill solution also provides double patterning support for back end layers and user-defined fill cells that are automatically inserted into a layout based on analysis of the design.

Reliability is also a key element of TSMC’s 16nm FinFET process technology. FinFET 3D transistors will enable devices with higher drive strengths than at previous nodes, so accurate reliability verification becomes even more critical. As highlighted in the Design Enablement section of the recent TSMC Technology Symposium, reliability checks based upon the Calibre PERC platform will enable customers to analyze and correct issues like electrostatic discharge (ESD) and latch-up.