Wednesday, May 22, 2013

ATopTech’s Aprisa and Apogee physical implementation tools certified by TSMC for 16nm FinFET technology

USA: ATopTech, the leader in next-generation physical design solutions that address the challenges of designing integrated circuits (ICs), announced that Aprisa and Apogee, the company’s place and route solution, have been certified by TSMC for 16nm FinFET v0.1 design enablement.

TSMC’s leading 16nm FinFET technology offers improved design performance, lower overall power, and smaller area.

Aprisa and Apogee were certified in October 2012 by TSMC for 20nm design enablement with double patterning technology (DPT) routing rule support for TSMC’s 20nm reference flow. Aprisa’s innovative color-aware DPT routing technology uses a correct-by-construction approach that guarantees no missing DPT violations at signoff while achieving excellent routability and router runtime.

Aprisa and Apogee has subsequently gone through a rigorous 16nm FinFET certification process that includes signoff correlation checking of design rule checking (DRC), layout versus schematic (LVS), and formal verification to fulfill new process requirements such as new design rules for P-80 layers, 16nm FinFET transistor-related placement rules and DFM requirements.

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