Atrenta and Mentor collaborate on SoC power signoff

DAC 2013, USA: Atrenta Inc. announced that it is collaborating with Mentor Graphics Corp. to enable accurate, signoff quality power estimation at the register transfer level (RTL) for the entire system on chip (SoC) device.

The project aims to radically improve SoC design efficiency by facilitating RTL power estimation for designs in excess of 50 million gates, running actual software scenarios over hundreds of millions cycles, resulting in large simulation data sets in excess of 10Gbytes.

The collaboration between the two companies has resulted in an interface between the Mentor Veloce2 emulator and Atrenta’s SpyGlass Power RTL power estimation tool to allow estimation of SoC power and validation of power budgets at the full-chip level.

The interface files from the emulator significantly differ from files generated by standard RTL simulation tools since they are optimized for large data sets over millions of cycles. The collaboration enables SpyGlass Power to consume specific data generated by Veloce2 in switching activity interface format (SAIF) and files system database (FSDB) industry formats.

Traditionally, RTL power estimation is performed at the block level due to the lack of full-chip SoC simulation data for accurate dynamic power estimation in the different functional modes of the chip. SoC power is then calculated by adding the power numbers of the sub-blocks.

The sum of the power of the blocks does not always correlate to the total power consumed by the chip due to the activity caused by complex interfaces between the sub-blocks. This often results in surprises during the final tapeout as the power budgets for the SoC can be way off.