SAN JOSE, USA: Cypress Semiconductor Corp. announced the immediate availability of its GPIF II Designer Software for EZ-USB FX3 Controllers for SuperSpeed USB 3.0.
GPIF (General Programmable Interface) II Designer provides designers with a powerful, easy-to-use graphical interface to configure EZ-USB FX3’s programmable GPIF II interface to communicate with any microcontroller, ASIC, FPGA, Image Sensor or similar devices that need USB connectivity. EZ-USB FX3 is the industry’s first and only certified programmable USB 3.0 device controller that adds USB SuperSpeed connectivity to virtually any system.
The tool provides an intuitive interface through just three easy-to-use screens: a Configuration Window to define I/O and control lines, a State Machine Canvas to define the interface’s state machine, and a Timing Simulation Window to verify interface timing. The tool also provides industry standard project management features for FX3 customers to save and reuse their GPIF II interface designs. The tool generates a C header file that can be integrated with FX3 applications using the FX3 API library and used with standard ARM tools.
“The GPIF II Designer is a key component of the FX3 development infrastructure,” stated Mark Fu, senior marketing director of Cypress’s USB 3.0 Business Unit. “The state machine-based approach used in the GPIF II Designer allows the user to design an interface in a matter of minutes using an easy-to-use bubble diagram approach. The combination of GPIF II Designer and the FX3 API Library provides a powerful platform for FX3 designers worldwide to reduce development time and accelerate time to market for SuperSpeed applications.”
GPIF II Designer comes bundled with ready-to-use customizable definitions for Asynchronous and Synchronous Slave FIFO, Asynchronous and Synchronous ADMUX, and Asynchronous SRAM interfaces. Designers who need one of these pre-defined interfaces in their system can easily adapt them to their own needs by choosing from a standard set of parameters including bus width (x8, x16, and x32), endianness, and clock settings.
Tuesday, March 6, 2012
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