Friday, February 17, 2012

Blue Pearl releases 6.0 of EDA software suite with SystemVerilog and FPGA enhancements

SAN JOSE, USA: Blue Pearl Software Inc, the provider of next generation EDA software that increases designer productivity and design quality, announced that it is shipping Release 6.0 of its EDA software, Blue Pearl Software Suite, for Windows and Linux operating systems. It includes enhancements that improve support for SystemVerilog and VHDL, as well as FPGA design.

“Our 6.0 Release improves support for SystemVerilog and VHDL and the FPGA synthesis flow,” said Shakeel Jeeawoody, director of Product Marketing at Blue Pearl. “Designers can now mix and match hardware languages in the same design, with language checking that matches their downstream tools.”

Blue Pearl Software Suite offers comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic Synopsys Design Constraints (SDC) generation for FPGA, ASIC and SOC designs. Its visualization and validation technology gives users immediate feedback for validating automatically generated timing constraints.

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