SuVolta discloses Deeply Depleted Channel technology structure at IEDM 2011

LOS GATOS, USA: SuVolta Inc., a developer of scalable low-power CMOS technologies, today disclosed details of its Deeply Depleted Channel (DDC) low-power transistor technology, to be presented at IEDM 2011.

SuVolta’s DDC technology – a component of its PowerShrink low-power CMOS platform – provides the industry with a low-power device technology that has been demonstrated to reduce power consumption by 50 percent without impacting operating speed. When coupled with advanced voltage scaling techniques, the DDC technology can reduce power consumption by 80 percent or even more.

“SuVolta’s technology, which we have proven in silicon, has generated a tremendous amount of interest in the semiconductor industry,” said Dr. Bruce McWilliams, president and CEO at SuVolta. “We are now disclosing the details of our DDC transistor technology so that the industry’s technologists can envision how SuVolta’s technology can lower power consumption, can allow lower supply voltage, and can enable process scaling to sub-20nm.”

SuVolta’s DDC transistor technology
SuVolta’s DDC transistor reduces threshold voltage (VT) variability and enables continued CMOS scaling. The structure works by forming a deeply depleted channel when a voltage is applied to the gate. In a typical implementation the DDC channel has several regions – an undoped or very lightly doped region, a VT setting offset region and a screening region. Each implementation of SuVolta’s DDC transistor may vary depending on the wafer fabrication facility and specific chip design requirements.Source: SuVolta, USA.

The undoped or very lightly doped region removes dopants from the channel which allows for a deeply depleted channel. This reduces random dopant fluctuation (RDF) thereby enabling VDD scaling and improved mobility for increased effective current.
The VT setting offset region sets the transistor threshold voltage levels, without degrading channel mobility. This region also improves sigma VT over conventional transistors.

The screening region screens the charge and sets the depletion layer depth. It also serves as a body for dynamic VT adjustment through biasing, if desired.

The DDC transistor enables lower power operation by reducing power supply voltage. By controlling VT variation, chips designed using SuVolta DDC technology can achieve a number of benefits including:
* 30 percent lower operating voltage with no performance impact;
* much lower leakage;
* less design “guard banding”; and
* improved yields.

In addition, DDC transistor allows for the setting of multipleVTs, which is vital for today’s low-power products. Besides the benefit of significant VT variation reduction, DDC transistors have additional benefits which lead to further reductions in power with higher speed. These include:
* increased channel mobility for increased drive current;
* reduced drain induced barrier loading (DIBL); and
* increased body coefficient for better VT control.

"There are times when making chips smaller just doesn’t make sense anymore. Increased lithography costs are inciting the end of Moore’s Law because the cost per transistor is plateauing. We are approaching that time now with 28nm and 20nm which I believe will be long-lived nodes,” said Dr. Scott Thompson, CTO at SuVolta. “Aside from microprocessors, most of the chips for the mobile market put a premium on cost control and low-power consumption. SuVolta’s DDC structure is unique in that it is the only transistor approach that is fully compatible with today’s CMOS process integration and fab facilities, and that enables semiconductor companies to retain their existing circuit intellectual property.”

“For the industry to enjoy continued advances in mobile electronics, core technology must keep advancing,” said Bill Joy, partner at Kleiner Perkins Caufield & Byers. “SuVolta has invented a breakthrough compatible planar bulk CMOS-based process technology to solve the semiconductor industry’s greatest challenge – power.”