Thursday, December 15, 2011

Process of FPGA design takes giant leap forward with Stellar IP tool from 4DSP

UK: 4DSP LLC takes another giant leap forward in simplifying the process of FPGA design by releasing their new Stellar IP tool. Stellar IP is designed to automate the creation of an FPGA image by reusing proven IP cores. It offers a platform for software engineers to target FPGA devices.

In recent years, the substantial growth of resources available inside FPGA devices has forced engineers to change the way they approach programmable logic design. A higher level of abstraction and the removal of error prone tasks are critical to the success and timely completion of projects.

FPGA technology has often been decried in the past for its implementation slowness from concept to release. Relying on existing IP to speed up this process has become essential and ensures that the FPGA portion of the system does not become the schedule bottleneck. Stellar IP does not claim it will solve all inherent problems of FPGA design but it guarantees that its simplicity of use will help engineers complete their project faster by removing tedious steps out the cycle.

Knowledge of a HDL language is not required for using Stellar IP. This provides software engineers with the ability to create new FPGA designs by relying on existing IP and extend their domain of influence to the entire system.

“Programming a software for a Stellar IP based design is as simple as using a microcontroller. Designing a StellarIP FPGA firmware is even easier since it’s only about interconnecting IP blocks to one another, either by using a text file or a graphical schematics editor. The tool takes care of the rest and prevents the user from having to deal with the intricacies of FPGA design,” said Arnaud Maye, Embedded Systems manager at 4DSP.

Stellar IP offers many benefits such as simplifying the integration of new cores that can be reused across multiple designs. It provides a library of off-the-shelf IP cores and it runs FPGA compilation tools with automated bitstream generation. It automates the creation of ISE project and simulation scripts. It also makes it possible for software engineers to implement FPGA designs.

This is a great opportunity for FPGA engineers to solidify thier FPGA firmware.

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