TSMC unveils first commercial 65nm multi-time programmable NVM technology

HSINCHU, TAIWAN: Taiwan Semiconductor Manufacturing Co. Ltd announced the foundry segment's first functional 65nm multi-time programmable (MTP) non-volatile memory (NVM) process technology.

The technology incorporates process-qualified MTP IP blocks jointly developed with Virage Logic. The new technology is the first 2.5 volt MTP process, breaking the heretofore 3.3 volt baseline barrier. It eliminates the need for an external EEPROM currently in many systems applications, thereby reducing power, area and costs while increasing data security.

Built on TSMC's 65nm Low Power (LP) process, the new MTP technology features up to 8k bits memory size that is ideal for small memory requirements associated with MP3 music downloadable digital rights management (DRM), fingerprint identification applications, RFID devices and prepaid cash or phone cards.

The 65nm MTP process is built up to 10 metal layers using copper low-k interconnects and nickel silicide transistor interconnects. The technology is fully logic-compatible and the NVM memory requires no additional processes or masks. Devices built using the process will support full read and program operations across temperatures ranging from -40 degrees C to 125 degrees C, with minimum 10-year data retention at 125 degrees C.

"With inputs from customers' design needs, we are convinced this 65nm process is well-suited for applications that require a small memory footprint on a leading edge manufacturing technology," explains Jason Chen, vice president Worldwide Sales and Marketing for TSMC.

"TSMC and Virage Logic have worked together on the 65nm MTP process to bring true multi-time NVM programmability to such market segments as security and wireless where advanced process adoption is crucial," said Dr. Yankin Tanurhan, vice president and general manager, NVM Solutions, Virage Logic.

"Because AEON is based on a standard logic CMOS process, it requires no additional masks or processes which eliminates the costly manufacturing steps normally involved with floating gate memory while reducing the engineering effort and associated costs of integrating NVM into SoC designs."