Cadence, Toshiba ally on integrated design environment for COT and SoC design

SAN JOSE, USA: Cadence Design Systems announced an extensive collaboration with Toshiba to address the challenges of existing and next-generation SoC designs.

Toshiba is a leading provider of process and design solution for cutting-edge SoC products. Based on the Cadence Encounter Digital Implementation System and the Cadence Virtuoso Custom Design Solution, the collaboration provides a full digital and mixed-signal design environment to Toshiba and its COT customers for the most advanced semiconductor products where integration of digital and mixed-signal designs is a key to success.

“In highly competitive markets such as wireless and consumer devices designers are expressing a growing requirement for integration of digital and mixed-signal content on ever-smaller semiconductor devices,” said Tatsuo Noguchi, Technology Executive for SoC of Toshiba Corp. Semiconductor Co.

“Because the Cadence Encounter and Virtuoso design environments provide the industry-leading analog and digital design flows necessary to meet these challenges, we are delighted to work closely with Cadence and help our COT customers realize their highly integrated custom IC design. We expect the collaboration to continue to provide benefits to the design community going forward.”

The ongoing collaboration focuses primarily on physical implementation, verification, and custom analog integration for COT and SoC designs. The physical implementation flow includes Cadence Encounter RTL Compiler, Cadence Conformal verification suite, Cadence QRC Extraction and the Encounter Digital Implementation System.

The Toshiba flow utilizes Cadence Encounter Timing System for timing verification, Cadence Physical Verification System for physical verification, Cadence Virtuoso IC 6.1 for custom analog design and Cadence process design kits (PDKs) for quicker, more accurate design.

“Cadence has worked extensively over the years with Toshiba Semiconductor to provide the design environment necessary to meet all the latest challenges to COT and SoC designs,” said Chi-Ping Hsu, senior vice president of the Implementation Products Group at Cadence. “We’re confident that this association will continue to deliver the design flows necessary to create high-quality semiconductor products.”