USA: DSP Group Inc.announced that its innovative XciteR VoIP chipset solution was chosen by InnoMedia for use in the company's residential analog telephone adapter (ATA) product line.
InnoMedia is an innovative manufacturer of IP voice/video telephony and broadband Enterprise SIP Gateway (ESG) products. A state-of-the-art, highly integrated system-on-a-chip solution (SoC), XciteR is ideal for the development of small, high-performing and feature-rich ATAs at low cost and fast time to market.
InnoMedia's single-port and 2-port residential ATAs enable legacy analog telephones, fax machines, conference telephones and other analog devices to access IP-based telephony services. Targeting small-to-medium enterprises (SMEs) and consumers, the VoIP ATA extends the value of investments in analog devices, while facilitating migration to richer, lower-priced DECT/CAT-iq based IP services.
Anchored by a high-performance ARM926(TM) application processor running Linux OS and a strong DSP processor, XciteR is suitable for developing multiple innovative VoIP endpoints. Providing the market's best price-performance as well as a myriad of embedded software features, including fax over IP (FoIP) and NAT routing, the chipset solution ensures minimal development investment and a low bill of materials (BOM).
Wednesday, March 6, 2013
Renesas intros second-gen USB 3.0-SATA3 bridge SoC with reduced external components
JAPAN: Renesas Electronics Corp. announced the availability of its new SuperSpeed Universal Serial Bus (USB 3.0) to Serial ATA (SATA) Revision 3 bridge SoC (system on chip,part number μPD720231) that enables the reduction of the total BOM significantly.
The uPD720231 enables effective multi-gigabit per second (Gbps) data transfer between a USB 3.0 host system and a SATA device used in widely adopted external USB hard drives and solid state drives (SSD).
USB 3.0 technology delivers more than 10 times the data transfer performance of the commonly used USB 2.0 peripheral interface. As the demand for media storage capacities and data transfer speed increases, the uPD720231 offers a fundamental building block to create an improved user experience for external USB storage.
Renesas Electronics has played a leading role both in defining USB standards and in developing USB technology. Renesas has enabled the USB 3.0 market by releasing the μPD720200 USB 3.0 host controller to mass production in June 2009. Since then, the company’s lineup of USB 3.0 host controllers has been widely adopted by customers worldwide. Total shipments of these products have already exceeded 62 million units.
In December 2009, the company also released a UASP driver that further enhances the data transfer for storage devices by improving the performance limit of the BOT (Bulk-Only Transfer) standard used by USB 2.0, making it possible for external storage devices to take advantage of the increased speed offered by the new USB 3.0 standard. To respond to the need for even faster data transfer performance necessary with the increased scale of the data in the storage device market, Renesas introduced the μPD720230 bridge SoC and confirmed USB-IF certification in 2011.
The new μPD720231 device was developed to respond to the need to reduce the number of components and to simplify printed circuit board (PCB) controller design.
The uPD720231 enables effective multi-gigabit per second (Gbps) data transfer between a USB 3.0 host system and a SATA device used in widely adopted external USB hard drives and solid state drives (SSD).
USB 3.0 technology delivers more than 10 times the data transfer performance of the commonly used USB 2.0 peripheral interface. As the demand for media storage capacities and data transfer speed increases, the uPD720231 offers a fundamental building block to create an improved user experience for external USB storage.
Renesas Electronics has played a leading role both in defining USB standards and in developing USB technology. Renesas has enabled the USB 3.0 market by releasing the μPD720200 USB 3.0 host controller to mass production in June 2009. Since then, the company’s lineup of USB 3.0 host controllers has been widely adopted by customers worldwide. Total shipments of these products have already exceeded 62 million units.
In December 2009, the company also released a UASP driver that further enhances the data transfer for storage devices by improving the performance limit of the BOT (Bulk-Only Transfer) standard used by USB 2.0, making it possible for external storage devices to take advantage of the increased speed offered by the new USB 3.0 standard. To respond to the need for even faster data transfer performance necessary with the increased scale of the data in the storage device market, Renesas introduced the μPD720230 bridge SoC and confirmed USB-IF certification in 2011.
The new μPD720231 device was developed to respond to the need to reduce the number of components and to simplify printed circuit board (PCB) controller design.
Xilinx solutions target growing ASIC and ASSP gaps for next-gen smarter networks and data centers
USA: Xilinx Inc. announced solutions for significant and growing gaps in ASIC and ASSP offerings targeting next-generation smarter networks and data centers.
In order to fill these gaps, Xilinx has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.
These solutions target customers who need to rapidly create, differentiate, and evolve intelligent, fabric-centric data centers and software defined networks (SDN), ‘many-band’ self-organizing networks (SON) for LTE and LTE Advanced wireless HetNets, and 400G and Nx100G OTN solutions with high availability, low latency, low jitter, and high Quality of Service (QoS) requirements.
“ASICs and ASSPs in applications like OTN have been disappearing at a surprisingly rapid pace due to the escalating cost of design, wide variance in device requirements, and the need for much greater levels of intelligence and adaptability,” said Krishna Rangasayee, senior VP and GM of the Xilinx Communication Business Unit. “We see these same pervasive trends spreading throughout next-generation wired and wireless networks and data centers. We also hear from our leading customers that the option for ‘me too’ equipment design has vanished.”
Addressing growing gaps with ASICs and ASSPs
Many ASIC and ASSP vendors are:
* Challenged to meet the combined requirements for intelligence, flexibility, and adaptability in next-generation systems.
* Struggling with fragmented and rapidly changing networking and data center standards and application demands.
* Incapable of enabling customers to effectively add differentiation through their own ‘secret sauce.’
These challenges coupled with the rapidly increasing IC design costs and lengthy design cycles have created significant solution gaps for customers. ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not an optimal fit for the target application, and/or provide limited ability for customers to differentiate their end products. Often customers face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.
SmartCORE IP building blocks for smarter systems
Xilinx SmartCORE IP – used in conjunction with the company’s ARM processor-based Zynq-7000 All Programmable SoCs, FPGAs, and 3D ICs – provides the technology foundation needed to create an extremely wide range of next-generation applications ranging from data center security appliances and resource-optimizing TOR (top-of-rack) switches to extremely efficient mobile backhaul modems and smarter wired access equipment.
SmartCORE IP-based solutions examples include, but are not limited to:
* “Service-level-aware,” packet-based processing solutions with dynamic QoS adjustment for 100G and greater OTN networks.
* Customizable DPD & CFR for Class 1 MC-GSM Power Amplifier Linearization with 60 MHz transmission bandwidth including integrated ARM processor-based control for LTE and LTE Advanced wireless radios.
* 80 Gbps data center NIC solutions with high-granularity traffic management, enabling the provisioning of a high number of traffic flows to accommodate new services and associated service monetization.
Customers and services add ‘secret sauce’
Customers can add their differentiating ‘secret sauce’ comprised of smarter, adaptable algorithms and functions by quickly assembling unique combinations of SmartCORE IP embodied in highly flexible Xilinx All Programmable devices. These differentiating elements can be implemented using programmable hardware and/or ARM processor-based programmable software.
Xilinx helps customers optimize their designs during the early architecture design phase with applications specialists, and offers advanced design services for customers who require IP customization or full system design support. In the last two-plus years, while Xilinx was acquiring and developing its smarter solutions and working with its most advanced customers, these offerings displaced more than 200 ASICs and ASSPs in a wide range of applications.
In order to fill these gaps, Xilinx has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.
These solutions target customers who need to rapidly create, differentiate, and evolve intelligent, fabric-centric data centers and software defined networks (SDN), ‘many-band’ self-organizing networks (SON) for LTE and LTE Advanced wireless HetNets, and 400G and Nx100G OTN solutions with high availability, low latency, low jitter, and high Quality of Service (QoS) requirements.
“ASICs and ASSPs in applications like OTN have been disappearing at a surprisingly rapid pace due to the escalating cost of design, wide variance in device requirements, and the need for much greater levels of intelligence and adaptability,” said Krishna Rangasayee, senior VP and GM of the Xilinx Communication Business Unit. “We see these same pervasive trends spreading throughout next-generation wired and wireless networks and data centers. We also hear from our leading customers that the option for ‘me too’ equipment design has vanished.”
Addressing growing gaps with ASICs and ASSPs
Many ASIC and ASSP vendors are:
* Challenged to meet the combined requirements for intelligence, flexibility, and adaptability in next-generation systems.
* Struggling with fragmented and rapidly changing networking and data center standards and application demands.
* Incapable of enabling customers to effectively add differentiation through their own ‘secret sauce.’
These challenges coupled with the rapidly increasing IC design costs and lengthy design cycles have created significant solution gaps for customers. ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not an optimal fit for the target application, and/or provide limited ability for customers to differentiate their end products. Often customers face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.
SmartCORE IP building blocks for smarter systems
Xilinx SmartCORE IP – used in conjunction with the company’s ARM processor-based Zynq-7000 All Programmable SoCs, FPGAs, and 3D ICs – provides the technology foundation needed to create an extremely wide range of next-generation applications ranging from data center security appliances and resource-optimizing TOR (top-of-rack) switches to extremely efficient mobile backhaul modems and smarter wired access equipment.
SmartCORE IP-based solutions examples include, but are not limited to:
* “Service-level-aware,” packet-based processing solutions with dynamic QoS adjustment for 100G and greater OTN networks.
* Customizable DPD & CFR for Class 1 MC-GSM Power Amplifier Linearization with 60 MHz transmission bandwidth including integrated ARM processor-based control for LTE and LTE Advanced wireless radios.
* 80 Gbps data center NIC solutions with high-granularity traffic management, enabling the provisioning of a high number of traffic flows to accommodate new services and associated service monetization.
Customers and services add ‘secret sauce’
Customers can add their differentiating ‘secret sauce’ comprised of smarter, adaptable algorithms and functions by quickly assembling unique combinations of SmartCORE IP embodied in highly flexible Xilinx All Programmable devices. These differentiating elements can be implemented using programmable hardware and/or ARM processor-based programmable software.
Xilinx helps customers optimize their designs during the early architecture design phase with applications specialists, and offers advanced design services for customers who require IP customization or full system design support. In the last two-plus years, while Xilinx was acquiring and developing its smarter solutions and working with its most advanced customers, these offerings displaced more than 200 ASICs and ASSPs in a wide range of applications.
EV Group extends wafer bonding equipment and process solutions for covalent bonding technology
USA: EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, is developing equipment and process technology to enable covalent bonds at room temperature.
This breakthrough technology will be available on a new equipment platform, called EVG580 ComBond, which will include process modules that are designed to perform surface preparation processes on both semiconductor materials and metals. EVG built on its decades of experience with plasma activated wafer bonding to create a novel process through which the treated surfaces form strong bonds at room temperature instantaneously without the need for annealing.
"In response to market needs for more sophisticated integration processes for combining materials with different coefficients of thermal expansion, we have developed a revolutionary process technology that enables the formation of bond interfaces between heterogeneous materials at room temperature," stated Markus Wimplinger, corporate technology development and IP director for EV Group. "Our unparalleled expertise in wafer bonding process technology will allow us to provide different variants of the new process according to the requirements of different substrate materials and applications."
EV Group's new process solutions will enable covalent combinations of compound semiconductors, other engineered substrates and heterogeneous materials integration for applications such as silicon photonics, high mobility transistors, high-performance/low-power logic devices and novel RF devices.
The process technology and equipment that enables this room temperature covalent wafer bonding will be applied to EVG's wafer bonding solutions for MEMS wafer-level packaging as well as to the integration of MEMS and CMOS devices.
Equipment systems based on a 200-mm modular platform, tailored for the specific needs of the new processes, will be available in 2013.
This breakthrough technology will be available on a new equipment platform, called EVG580 ComBond, which will include process modules that are designed to perform surface preparation processes on both semiconductor materials and metals. EVG built on its decades of experience with plasma activated wafer bonding to create a novel process through which the treated surfaces form strong bonds at room temperature instantaneously without the need for annealing.
"In response to market needs for more sophisticated integration processes for combining materials with different coefficients of thermal expansion, we have developed a revolutionary process technology that enables the formation of bond interfaces between heterogeneous materials at room temperature," stated Markus Wimplinger, corporate technology development and IP director for EV Group. "Our unparalleled expertise in wafer bonding process technology will allow us to provide different variants of the new process according to the requirements of different substrate materials and applications."
EV Group's new process solutions will enable covalent combinations of compound semiconductors, other engineered substrates and heterogeneous materials integration for applications such as silicon photonics, high mobility transistors, high-performance/low-power logic devices and novel RF devices.
The process technology and equipment that enables this room temperature covalent wafer bonding will be applied to EVG's wafer bonding solutions for MEMS wafer-level packaging as well as to the integration of MEMS and CMOS devices.
Equipment systems based on a 200-mm modular platform, tailored for the specific needs of the new processes, will be available in 2013.
Tuesday, March 5, 2013
TI and 4DSP collaborate on FPGA mezzanine card
USA: Texas Instruments Inc. (TI) and 4DSP, an innovative company specializing in low power, low weight and compact FPGA-based signal and image processing systems, announced their collaboration on a new mezzanine card, the FMC667, for mission critical applications.
4DSP's FMC667 mezzanine card, based on the emerging FMC form factor, includes TI's KeyStone-based TMS320C6678 multicore digital signal processor (DSP), DRAM memory and peripherals. With TI's high-performance C6678 multicore DSP, the FMC667 is able to more effectively and rapidly meet the essential requirements of Commercial Off-The-Shelf (COTS)-based systems, as well as increase processing power, accuracy and finer resolution in mission critical and industrial applications.
"TI's multicore software development kit made it easy for us to develop support libraries for our FMC667 card," said Arnaud Maye , Embedded Software manager at 4DSP. "With eight 1.25 GHz cores in parallel and the built-in capability to be a PCIe root complex, TI's C6678 DSP affirms itself as a control and high-end processing node for the most demanding applications."
4DSP's FMC667 card is primarily intended to be used in applications where an FPGA and DSP act as a co-processor of one another, such as video, telecom infrastructure, imaging, medical and wireless infrastructure markets. Mechanically and electrically compliant to the FMC standard (ANSI/VITA 57.1), the FMC667 module has a high-pin count connector and can be used in a conduction-cooled environment. Additionally, the card is also equipped with power supply and temperature monitoring, offering several power-down modes to switch off unused functions and peripheral interfaces.
Functionality, reliability and precision are vital factors mission critical developers must take into consideration when designing quality system applications. TI's C6678 multicore DSPs deliver the industry's first 10 GHz DSP with fixed- and floating-point performance on a single device for increased precision, a key requirement for mission critical systems.
Additionally, the C6678 multicore DSPs increase system capabilities by consolidating the functionality of multiple DSPs onto a single device, saving board space and cost and alleviating the challenge of size, weight and power (SwaP), as well as reducing overall clock rates and power consumptions.
The FMC667 mezzanine card will be available on March 15.
4DSP's FMC667 mezzanine card, based on the emerging FMC form factor, includes TI's KeyStone-based TMS320C6678 multicore digital signal processor (DSP), DRAM memory and peripherals. With TI's high-performance C6678 multicore DSP, the FMC667 is able to more effectively and rapidly meet the essential requirements of Commercial Off-The-Shelf (COTS)-based systems, as well as increase processing power, accuracy and finer resolution in mission critical and industrial applications.
"TI's multicore software development kit made it easy for us to develop support libraries for our FMC667 card," said Arnaud Maye , Embedded Software manager at 4DSP. "With eight 1.25 GHz cores in parallel and the built-in capability to be a PCIe root complex, TI's C6678 DSP affirms itself as a control and high-end processing node for the most demanding applications."
4DSP's FMC667 card is primarily intended to be used in applications where an FPGA and DSP act as a co-processor of one another, such as video, telecom infrastructure, imaging, medical and wireless infrastructure markets. Mechanically and electrically compliant to the FMC standard (ANSI/VITA 57.1), the FMC667 module has a high-pin count connector and can be used in a conduction-cooled environment. Additionally, the card is also equipped with power supply and temperature monitoring, offering several power-down modes to switch off unused functions and peripheral interfaces.
Functionality, reliability and precision are vital factors mission critical developers must take into consideration when designing quality system applications. TI's C6678 multicore DSPs deliver the industry's first 10 GHz DSP with fixed- and floating-point performance on a single device for increased precision, a key requirement for mission critical systems.
Additionally, the C6678 multicore DSPs increase system capabilities by consolidating the functionality of multiple DSPs onto a single device, saving board space and cost and alleviating the challenge of size, weight and power (SwaP), as well as reducing overall clock rates and power consumptions.
The FMC667 mezzanine card will be available on March 15.
Dongbu HiTek and Cortus to develop joint platform solution for MCU market
FRANCE & KOREA: Cortus, a technology leader in cost effective, silicon efficient, 32-bit processor IP, and speciality foundry Dongbu HiTek, are teaming up to offer platform solutions. The design platforms will be based on the Dongbu HiTek 0.13µm eFlash technology and energy efficient Cortus APS3R processor and peripheral IP.
Cortus S.A. licenses a range of 32-bit processor cores for embedded systems. The cores provide licensees with a scalable choice in embedded computational performance and silicon area to meet a wide variety of application needs.
“Our joint platform solution will be a compelling offering for the new wave of intelligent applications” says Dr. T.S. Kim, VP of Technical Engineering at Dongbu HiTek, “The Cortus APS3R processor is a great complement to our flash memory technology. Our platform will be optimized for the microcontroller (MCU) market.”
“We are delighted to team up with Dongbu HiTek”, says Michael Chapman, CEO and president of Cortus, “Their speciality foundry expertise with embedded flash memory is ideal for many of our target applications. By developing a joint platform we will accelerate time to market for developers of microcontroller ICs.”
The Cortus family of APS processors starts with the world’s smallest 32-bit core, the APS1, and goes up to the floating point FPS6. All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OSII and μCLinux.
Cortus S.A. licenses a range of 32-bit processor cores for embedded systems. The cores provide licensees with a scalable choice in embedded computational performance and silicon area to meet a wide variety of application needs.
“Our joint platform solution will be a compelling offering for the new wave of intelligent applications” says Dr. T.S. Kim, VP of Technical Engineering at Dongbu HiTek, “The Cortus APS3R processor is a great complement to our flash memory technology. Our platform will be optimized for the microcontroller (MCU) market.”
“We are delighted to team up with Dongbu HiTek”, says Michael Chapman, CEO and president of Cortus, “Their speciality foundry expertise with embedded flash memory is ideal for many of our target applications. By developing a joint platform we will accelerate time to market for developers of microcontroller ICs.”
The Cortus family of APS processors starts with the world’s smallest 32-bit core, the APS1, and goes up to the floating point FPS6. All cores interface to Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. They also share the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OSII and μCLinux.
CMX7011 digital voice processor gains voice store/retrieve and packet data function
UK: CML Microcircuits has released a new function image and datasheet for the CMX7011 digital voice processor. With the new function image, the CMX7011 is capable of voice store/retrieve (VSR) and packet data functionality.
The CMX7011 is a flexible, half-duplex, digital voice processor that provides the digital advantage to conventional analogue two-way radios. The device is specifically designed to implement secure digital voice scrambling on conventional analogue PMR radios and wireless door access and gate entry systems. In addition to digital voice encryption:
Function image: 7011FI-1.0.3.0
* The voice store and retrieve function offers storage of a minimum of 20 seconds of vocoded speech in receive mode. The recorded speech can be played back, paused, resumed, or erased so that memory can be reused. VSR also includes a step-back feature which allows the device to step back in discrete steps during playback mode.
* The packet data operation allows the device to send packetised data with CRC, FEC and interleaving, as a complete transaction. The only host intervention required is to specify the length of the data packet, transfer it into the device’s buffer, and instruct the device to transmit.
Key product benefits include:
* Added voice store and retrieve functionality.
* Added packet data functionality.
* Secure digital voice for analog PMR, wireless door access and gate entry systems.
* Simple integration directly into the radio audio path.
* Integrated RALCWI vocoder (royalty free).
* Robust embedded audio-band data modem.
* Small low-power 48-pin VQFN/LQFP package.
The CMX7011 is a flexible, half-duplex, digital voice processor that provides the digital advantage to conventional analogue two-way radios. The device is specifically designed to implement secure digital voice scrambling on conventional analogue PMR radios and wireless door access and gate entry systems. In addition to digital voice encryption:
Function image: 7011FI-1.0.3.0
* The voice store and retrieve function offers storage of a minimum of 20 seconds of vocoded speech in receive mode. The recorded speech can be played back, paused, resumed, or erased so that memory can be reused. VSR also includes a step-back feature which allows the device to step back in discrete steps during playback mode.
* The packet data operation allows the device to send packetised data with CRC, FEC and interleaving, as a complete transaction. The only host intervention required is to specify the length of the data packet, transfer it into the device’s buffer, and instruct the device to transmit.
Key product benefits include:
* Added voice store and retrieve functionality.
* Added packet data functionality.
* Secure digital voice for analog PMR, wireless door access and gate entry systems.
* Simple integration directly into the radio audio path.
* Integrated RALCWI vocoder (royalty free).
* Robust embedded audio-band data modem.
* Small low-power 48-pin VQFN/LQFP package.
After slowdown in 2012 global semiconductor market predicted to grow 4.5 percent in 2013
USA: After experiencing a slowdown in 2012 the global semiconductor market is set for growth. The World Semiconductor Trade Statistics (WSTS) predicts the global semiconductor market to grow by 4.5 percent in 2013 after declining 3.2 percent in 2012.
The SPDR S&P Semiconductor ETF (XSD) has gained over 7 percent year-to-date.
The global semiconductor industry posted total sales of $291.6 billion in 2012, according to the Semiconductor Industry Association. The total was the third highest ever, but a decline of 2.7 from the record $299.5 billion set in 2011.
The industry began to show some strength in the fourth quarter as it posted sales of $74.2 billion, which was a year-over-year increase of 3.8 percent.
"Despite substantial macroeconomic challenges, the global semiconductor industry outperformed forecasts and posted one of its highest yearly sales totals in 2012," said Brian Toohey, president and CEO, Semiconductor Industry Association. "Recent momentum, led by strength in the Americas, has the industry well-positioned for a successful 2013."
The SPDR S&P Semiconductor ETF (XSD) has gained over 7 percent year-to-date.
The global semiconductor industry posted total sales of $291.6 billion in 2012, according to the Semiconductor Industry Association. The total was the third highest ever, but a decline of 2.7 from the record $299.5 billion set in 2011.
The industry began to show some strength in the fourth quarter as it posted sales of $74.2 billion, which was a year-over-year increase of 3.8 percent.
"Despite substantial macroeconomic challenges, the global semiconductor industry outperformed forecasts and posted one of its highest yearly sales totals in 2012," said Brian Toohey, president and CEO, Semiconductor Industry Association. "Recent momentum, led by strength in the Americas, has the industry well-positioned for a successful 2013."
Monday, March 4, 2013
Cu pillar and micro-bumping re-invigorate Flip-Chip market, enabling it to grow at 19 percent
FRANCE: Yole Développement has announced its Flip Chip Market and Technology Trends report. Yole's analysis updates the business status of the Flip-Chip market including data for TIM, underfills, substrates and Flip-Chip bonders.
Over the next five years, an incredible 3x wafer growth is expected for the Flip-Chip platform, which will reach 40 million+ of 12’’eq wspy by 2018!
Despite its high 19 percent CAGR, Flip-chip is not new - in fact, it was first introduced by IBM over 30 years ago! As such, it would be easy to consider it an old, uninteresting, mature technology… but this is far from true! Instead, Flip-Chip is keeping up with the times and developing new bumping solutions to serve the most advanced technologies, like 3DIC and 2.5D.
Indeed, no matter what packaging technology you’re using, a bumping step is always required at the end! In 2012, bumping technologies accounted for 81 percent of the total installed capacity in the middle end area. That’s big. Really big. So big that it represents 14 million+ 12’’eq wafers - and fab loading rates are high as well, especially for the Cu pillar platform (88 percent).
Flip-Chip is also big on value: in 2012 it was a $20 billion market (making it the biggest market in the middle-end area), and Yole Développement expects it to continue growing at an 9 percent clip, ultimately reaching $35 billion by 2018!
Flip-Chip capacity is expected to grow over the next five years to meet large demand from three main areas:
1) CMOS 28nm IC, including new applications like APE and BB.
2) The next generation of DDR memory.
3) 3DIC/2.5D interposer using micro-bumping.
Driven by these applications, Cu pillar is on its way to becoming the interconnect of choice for Flip-Chip.
In addition to traditional applications which have used Flip-Chip for a while now (laptop, desktop and their CPUs, GPUs and chipsets - which are growing slowly but still represent significant production volumes for Flip-Chip), Yole Développement’s analyst expects to see strong demand from mobile and wireless (smartphones), consumer applications (tablets, smart TV, set top box), computing and high performance/ industrial applications such as network, servers, data centers and HPC.
The new “Flip-Chip packaged ICs” are expected to radically alter the market landscape with new specific motivations that will drive demand for wafer bumping. “In the context of 3D integration and the “More than Moore” approach, Flip-Chip is one of the key technology bricks and will help enable more sophisticated system on chip integration than ever before!”, says Lionel Cadix, Market and Technology analyst, Advanced Packaging, at Yole.
Flip-Chip is being reshaped by a new kind of demand that is hungry for Cu pillars and micro-bumps, which are on their way to becoming the new mainstream bumping metallurgy for die interconnection.
Meanwhile, Cu pillar is fast becoming the interconnect of choice for advanced CMOS (≤ 28nm), memory, and micro-bumping for 2.5D interposer and 3DIC.
In addition to studying mainstream bumping technologies, this Yole Développement report focuses on Cu pillar bumping, which is becoming increasingly popular for a wide variety of applications. The massive adoption of Cu pillars is motivated by a combination of several drivers, including very fine pitch, no UBM needed, high Z standoff, etc.
Cu pillar Flip-Chip is expected to grow at a 35 percent CAGR between 2010-2018 in terms of wafer count. Production is already high at Intel, the #1 Flip-Chip producer - and by 2014, more than 50 percent of bumped wafers for Flip-Chip will be equipped with Cu pillars.
As early as 2013, micro-bumping for 2.5D and 3D IC, in conjunction with new applications like APE, DDR memory, etc., will boost Flip-Chip demand and create new challenges and new technological developments (see figure on the left). Today, Flip- Chip is available in a wide range of pitches to answer the specific needs of every application.
The ultimate evolution in bumping technologies will consist of directly bonding IC with copper pads. 3D integration of ICs using this bump-less Cu-Cu bonding is expected to provide an IC-to-IC connection density higher than 4 x 105 cm-2, making it suitable for future wafer-level 3D integration of IC in order to augment Moore’s Law scaling.
The major OSATs are preparing to produce fcBGA based Cu pillar packages and won’t limit the reach of cu pillar bumping to fcCSP. This will allow every company involved in CPU, GPU Chipset, APE, BB, ASIC, FPGA and Memory to access Cu pillar Flip-Chip technology.
Cu pillar capacity is expected to grow rapidly over the 2010-2014 timeframe (31 percent CAGR), hitting ~ 9M wspy by 2014 and supporting the growing demand for micro-bumping and advanced CMOS IC bumping.
In the mutating middle-end area, CMOS foundries now propose wafer bumping services (TSMC, GLOBALFOUNDRIES, etc.), as opposed to bumping houses, which are dedicated to bumping operations (FCI, Nepes, etc.), and OSATs, which keep investing in advanced bumping technologies.
In 2012, OSATs owned 31 percent of installed capacity in ECD solder bumping and 22 percent of installed capacity in Cu pillar bumping. A full overview of 2012 installed capacities for all bumping platforms is provided in this report.
Concerning geography, Taiwan has the biggest overall bumping capacity (regardless of the metallurgy), with important capacity coming from foundries and OSAT factories. Taiwan currently leads the outsourcing “solder and copper” Flip-Chip wafer bumping market.
Flip-Chip market growth, spurred on by the emergence of the “middle-end” environment, has challenged traditional “IDM vs. fabless” supply chain possibilities more than ever before!
Over the next five years, an incredible 3x wafer growth is expected for the Flip-Chip platform, which will reach 40 million+ of 12’’eq wspy by 2018!
Despite its high 19 percent CAGR, Flip-chip is not new - in fact, it was first introduced by IBM over 30 years ago! As such, it would be easy to consider it an old, uninteresting, mature technology… but this is far from true! Instead, Flip-Chip is keeping up with the times and developing new bumping solutions to serve the most advanced technologies, like 3DIC and 2.5D.
Indeed, no matter what packaging technology you’re using, a bumping step is always required at the end! In 2012, bumping technologies accounted for 81 percent of the total installed capacity in the middle end area. That’s big. Really big. So big that it represents 14 million+ 12’’eq wafers - and fab loading rates are high as well, especially for the Cu pillar platform (88 percent).
Flip-Chip is also big on value: in 2012 it was a $20 billion market (making it the biggest market in the middle-end area), and Yole Développement expects it to continue growing at an 9 percent clip, ultimately reaching $35 billion by 2018!
1) CMOS 28nm IC, including new applications like APE and BB.
2) The next generation of DDR memory.
3) 3DIC/2.5D interposer using micro-bumping.
Driven by these applications, Cu pillar is on its way to becoming the interconnect of choice for Flip-Chip.
In addition to traditional applications which have used Flip-Chip for a while now (laptop, desktop and their CPUs, GPUs and chipsets - which are growing slowly but still represent significant production volumes for Flip-Chip), Yole Développement’s analyst expects to see strong demand from mobile and wireless (smartphones), consumer applications (tablets, smart TV, set top box), computing and high performance/ industrial applications such as network, servers, data centers and HPC.
The new “Flip-Chip packaged ICs” are expected to radically alter the market landscape with new specific motivations that will drive demand for wafer bumping. “In the context of 3D integration and the “More than Moore” approach, Flip-Chip is one of the key technology bricks and will help enable more sophisticated system on chip integration than ever before!”, says Lionel Cadix, Market and Technology analyst, Advanced Packaging, at Yole.
Flip-Chip is being reshaped by a new kind of demand that is hungry for Cu pillars and micro-bumps, which are on their way to becoming the new mainstream bumping metallurgy for die interconnection.
Meanwhile, Cu pillar is fast becoming the interconnect of choice for advanced CMOS (≤ 28nm), memory, and micro-bumping for 2.5D interposer and 3DIC.
In addition to studying mainstream bumping technologies, this Yole Développement report focuses on Cu pillar bumping, which is becoming increasingly popular for a wide variety of applications. The massive adoption of Cu pillars is motivated by a combination of several drivers, including very fine pitch, no UBM needed, high Z standoff, etc.
Cu pillar Flip-Chip is expected to grow at a 35 percent CAGR between 2010-2018 in terms of wafer count. Production is already high at Intel, the #1 Flip-Chip producer - and by 2014, more than 50 percent of bumped wafers for Flip-Chip will be equipped with Cu pillars.
As early as 2013, micro-bumping for 2.5D and 3D IC, in conjunction with new applications like APE, DDR memory, etc., will boost Flip-Chip demand and create new challenges and new technological developments (see figure on the left). Today, Flip- Chip is available in a wide range of pitches to answer the specific needs of every application.
The ultimate evolution in bumping technologies will consist of directly bonding IC with copper pads. 3D integration of ICs using this bump-less Cu-Cu bonding is expected to provide an IC-to-IC connection density higher than 4 x 105 cm-2, making it suitable for future wafer-level 3D integration of IC in order to augment Moore’s Law scaling.
The major OSATs are preparing to produce fcBGA based Cu pillar packages and won’t limit the reach of cu pillar bumping to fcCSP. This will allow every company involved in CPU, GPU Chipset, APE, BB, ASIC, FPGA and Memory to access Cu pillar Flip-Chip technology.
Cu pillar capacity is expected to grow rapidly over the 2010-2014 timeframe (31 percent CAGR), hitting ~ 9M wspy by 2014 and supporting the growing demand for micro-bumping and advanced CMOS IC bumping.
In the mutating middle-end area, CMOS foundries now propose wafer bumping services (TSMC, GLOBALFOUNDRIES, etc.), as opposed to bumping houses, which are dedicated to bumping operations (FCI, Nepes, etc.), and OSATs, which keep investing in advanced bumping technologies.
In 2012, OSATs owned 31 percent of installed capacity in ECD solder bumping and 22 percent of installed capacity in Cu pillar bumping. A full overview of 2012 installed capacities for all bumping platforms is provided in this report.
Concerning geography, Taiwan has the biggest overall bumping capacity (regardless of the metallurgy), with important capacity coming from foundries and OSAT factories. Taiwan currently leads the outsourcing “solder and copper” Flip-Chip wafer bumping market.
Flip-Chip market growth, spurred on by the emergence of the “middle-end” environment, has challenged traditional “IDM vs. fabless” supply chain possibilities more than ever before!
Fairchild's BLDC/PMSM motor controller with parallel processing cores provides simple conversion of AC motor control designs
USA: Motor control application designers are now moving away from the traditional universal or AC motor design to a more sophisticated brushless DC (BLDC) motor or permanent magnet synchronous motor (PMSM) design.
However, choosing either of these methods can be challenging if the designer has limited access to advanced, complex motor control algorithms. This can lead to significant spending of research and development resources and longer design times.
To help designers with these cost and software burdens, Fairchild Semiconductor has developed the FCM8531 analog and digital integrated motor controller. The FCM8531 is a tailored configurable solution complete with user guides, reference designs, and evaluation boards that help motor control designers shorten time-to-market and minimize software design efforts.
The FCM8531 is a three-phase, hybrid BLDC/PMSM controller with two parallel processors – an advanced motor controller (AMC) and an embedded microcontroller (MCU) – that provides a complete, one-chip solution for complex motor control applications.
The two core processors work independently but collaboratively to exchange data through an internal communications interface that helps to avoid system hang-ups and improves hardware protection. The FCM8531 minimizes the software burden with its integrated hardware controller and MCU interface management and achieves a fast load-response motor system with increased efficiency.
However, choosing either of these methods can be challenging if the designer has limited access to advanced, complex motor control algorithms. This can lead to significant spending of research and development resources and longer design times.
To help designers with these cost and software burdens, Fairchild Semiconductor has developed the FCM8531 analog and digital integrated motor controller. The FCM8531 is a tailored configurable solution complete with user guides, reference designs, and evaluation boards that help motor control designers shorten time-to-market and minimize software design efforts.
The FCM8531 is a three-phase, hybrid BLDC/PMSM controller with two parallel processors – an advanced motor controller (AMC) and an embedded microcontroller (MCU) – that provides a complete, one-chip solution for complex motor control applications.
The two core processors work independently but collaboratively to exchange data through an internal communications interface that helps to avoid system hang-ups and improves hardware protection. The FCM8531 minimizes the software burden with its integrated hardware controller and MCU interface management and achieves a fast load-response motor system with increased efficiency.
TowerJazz releases rule decks for advanced ESD and power domain checking using Mentor’s Calibre PERC
ISRAEL & USA: TowerJazz, the global specialty foundry leader, has announced the Mentor’s Calibre PERC rule decks are now available for TowerJazz customers to perform circuit reliability verification for its latest 0.18 micron products, including highly customized electrostatic discharge (ESD) and power management circuit checks.
Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (netlist) and physical layout information.
The Calibre PERC checks include: ESD CDM verification confirming that the transistor gate is not connected directly to a PAD, ESD protection on the IO PAD, and power management propagation rules to avoid HV signals connected to a low voltage device or domain.
For each one of the above, TowerJazz implemented a topological check as well as a specific layout DRC. During 2013, the design kit will be further enhanced to include comprehensive rule checks to support mutual customers with the most advanced deck. The 0.13 technology release will be available upon customer demand.
“TowerJazz is using Calibre PERC technology to help our customers achieve their reliability objectives by providing rule decks that perform advanced checks during signoff,” said Ori Galzur, VP of the TowerJazz VLSI Design Center.
“Our advanced design kits implement special ESD rules, charge device modeling (CDM), and power management propagation checks related to our specific technology. By eliminating many potential reliability issues at the design stage, the TowerJazz solution helps shorten time to market and drive long-term product success for our customers.”
“Customers are demanding higher reliability in all types of electronic products using complex ICs, from automobiles to mobile phones,” said Carey Robertson, director of Product Marketing for Calibre Circuit Verification at Mentor Graphics. “The Calibre PERC platform provides circuit reliability checking technology that goes beyond the scope of traditional DRC and ERC tools, so designers and foundries can implement highly complex checks that are customized to specific design styles and foundry manufacturing processes.”
Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (netlist) and physical layout information.
The Calibre PERC checks include: ESD CDM verification confirming that the transistor gate is not connected directly to a PAD, ESD protection on the IO PAD, and power management propagation rules to avoid HV signals connected to a low voltage device or domain.
For each one of the above, TowerJazz implemented a topological check as well as a specific layout DRC. During 2013, the design kit will be further enhanced to include comprehensive rule checks to support mutual customers with the most advanced deck. The 0.13 technology release will be available upon customer demand.
“TowerJazz is using Calibre PERC technology to help our customers achieve their reliability objectives by providing rule decks that perform advanced checks during signoff,” said Ori Galzur, VP of the TowerJazz VLSI Design Center.
“Our advanced design kits implement special ESD rules, charge device modeling (CDM), and power management propagation checks related to our specific technology. By eliminating many potential reliability issues at the design stage, the TowerJazz solution helps shorten time to market and drive long-term product success for our customers.”
“Customers are demanding higher reliability in all types of electronic products using complex ICs, from automobiles to mobile phones,” said Carey Robertson, director of Product Marketing for Calibre Circuit Verification at Mentor Graphics. “The Calibre PERC platform provides circuit reliability checking technology that goes beyond the scope of traditional DRC and ERC tools, so designers and foundries can implement highly complex checks that are customized to specific design styles and foundry manufacturing processes.”
Global semiconductor sales increase in January year-over-year
USA: The Semiconductor Industry Association (SIA), representing US leadership in semiconductor manufacturing and design, today announced that worldwide sales of semiconductors reached $24.05 billion for the month of January 2013, an increase of 3.8 percent from January 2012 when sales were $23.16 billion.
Global sales from January 2013 were 2.8 percent lower than the December 2012 total of $24.74 billion, reflecting normal seasonal trends. Regionally, the Americas posted its highest sales total of any January in the last decade. All monthly sales numbers represent a three-month moving average.
"Led by continuing strength in the Americas, the global semiconductor industry has built on its momentum from the end of 2012 with an encouraging start to 2013, but ongoing economic uncertainty is holding back more robust growth," said Brian Toohey, president and CEO, Semiconductor Industry Association.
"The across-the-board spending cuts that hit last week and the threat of a government shutdown later this month are just the latest examples of fiscal disruptions that sidetrack economic growth. Congress and the Administration must work together to get our country's fiscal house in order to restore confidence in the U.S. economy and spur growth."
Regionally, year-over-year sales increased in the Americas (10.5 percent) and Asia Pacific (7.8 percent), but decreased in Europe (-4.9 percent) and Japan (-12.3 percent). Sales increased modestly in Europe (0.4 percent) compared to the previous month, but decreased in Asia Pacific (-2.5 percent), the Americas (-3.5 percent) and Japan (-5.5 percent). January sales historically are lower than December sales due to seasonal trends.
Global sales from January 2013 were 2.8 percent lower than the December 2012 total of $24.74 billion, reflecting normal seasonal trends. Regionally, the Americas posted its highest sales total of any January in the last decade. All monthly sales numbers represent a three-month moving average.
"The across-the-board spending cuts that hit last week and the threat of a government shutdown later this month are just the latest examples of fiscal disruptions that sidetrack economic growth. Congress and the Administration must work together to get our country's fiscal house in order to restore confidence in the U.S. economy and spur growth."
Regionally, year-over-year sales increased in the Americas (10.5 percent) and Asia Pacific (7.8 percent), but decreased in Europe (-4.9 percent) and Japan (-12.3 percent). Sales increased modestly in Europe (0.4 percent) compared to the previous month, but decreased in Asia Pacific (-2.5 percent), the Americas (-3.5 percent) and Japan (-5.5 percent). January sales historically are lower than December sales due to seasonal trends.
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