TowerJazz releases rule decks for advanced ESD and power domain checking using Mentor’s Calibre PERC

ISRAEL & USA: TowerJazz, the global specialty foundry leader, has announced the Mentor’s Calibre PERC rule decks are now available for TowerJazz customers to perform circuit reliability verification for its latest 0.18 micron products, including highly customized electrostatic discharge (ESD) and power management circuit checks.

Many of these checks have been automated for the first time by taking advantage of the Calibre PERC product’s unique ability to combine schematic (netlist) and physical layout information.

The Calibre PERC checks include: ESD CDM verification confirming that the transistor gate is not connected directly to a PAD, ESD protection on the IO PAD, and power management propagation rules to avoid HV signals connected to a low voltage device or domain.

For each one of the above, TowerJazz implemented a topological check as well as a specific layout DRC. During 2013, the design kit will be further enhanced to include comprehensive rule checks to support mutual customers with the most advanced deck. The 0.13 technology release will be available upon customer demand.

“TowerJazz is using Calibre PERC technology to help our customers achieve their reliability objectives by providing rule decks that perform advanced checks during signoff,” said Ori Galzur, VP of the TowerJazz VLSI Design Center.

“Our advanced design kits implement special ESD rules, charge device modeling (CDM), and power management propagation checks related to our specific technology. By eliminating many potential reliability issues at the design stage, the TowerJazz solution helps shorten time to market and drive long-term product success for our customers.”

“Customers are demanding higher reliability in all types of electronic products using complex ICs, from automobiles to mobile phones,” said Carey Robertson, director of Product Marketing for Calibre Circuit Verification at Mentor Graphics. “The Calibre PERC platform provides circuit reliability checking technology that goes beyond the scope of traditional DRC and ERC tools, so designers and foundries can implement highly complex checks that are customized to specific design styles and foundry manufacturing processes.”