Wednesday, March 20, 2013

Truechip partners with Avant to market verification IP products in Asia

INDIA: Avant Technology has partnered with Truechip Solutions to bring the "verification IPs", into the Asia market.

Verification intellectual property (VIP) is the verification model and overall environment, which aids designers and verification engineers in the task of validating the functionality of their design.

The verification IP (VIP) is used in all levels of simulation-based verification. VIPs are based on standard protocols used in networking, automotive, computer and system designs, such as MIPI, USB, AMBA buses etc. These components are pre-verified to the standard protocols and contain the necessary infrastructure for testbench generation and checking mechanisms as well as all the appropriate routines to create individual protocols, commonly known as Bus Functional Models (BFM).

VIPs also include a strong protocol checking bus monitors which snoop all activity on the bus and raise alarm in case of protocol violations, in addition to providing statistics of the transactions.

"Avant Technology is a well-known distributor in Asia for leading edge technology solutions. It is important for Truechip to have highly competent and proactive distributor in Asia region. Asia region is critical mission points to expand our Verification IPs across the world" said Nitin Kishore, Engineering director, Truechip. "We are very pleased with our collaboration with Avant Technology. I think this can be attributed to their unique business model of bringing synergistic technologies together for the benefit of our mutual customers."

"I am very pleased that Truechip has chosen Avant Technology to support the sales promotion of its verification IPs," said Dr. Yao-Chang Chang, GM of Avant. "VIPs deliver what verification engineers need, Truechip's verification IP provides an effective and efficient way to verify the components interfacing with industry standard protocols in an ASIC/FPGA or SoC. Most important capabilities are debug features, lower footprint, and wide variety of error injection scenarios, which enables design teams to meet or exceed their ever shrinking design cycles."

Verification IP components provide enhanced productivity to the system and ASIC designers by reducing the time to create the verification infrastructure and testbench environment, including the required models. The verification IP based on System Verilog (HVL) allows verification and design teams to quickly and easily create random scenarios.

They also allow users to easily create directed test scenarios and test sequences for their designs. These test cases greatly aid users in finding functional bugs early in design cycle, hence reducing the
overall verification time.

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