ARM and Synopsys to deliver optimized reference implementations for ARM processors

USA & ENGLAND: ARM and Synopsys announced the availability of optimized 28-nanometer (nm) Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters as well as the CoreLink CCI-400 cache-coherent interconnect.

The companies collaborated to deliver these optimized implementations in TSMC 28HPM process technology using the Synopsys Galaxy Implementation Platform, ARM Artisan standard cells and memories, and ARM POP technology for core-hardening acceleration specifically optimized for Cortex-A15 and Cortex-A7 processor implementations.

System-on-a-chip (SoC) designers can use these Reference Implementations to create high-performance Cortex-A15 and energy-efficient Cortex-A7 processor clusters, and can combine them with the CCI-400 interconnect to create a big.LITTLE processing system that delivers increased product functionality with longer battery life.

"With a diverse range of products expected in today's end markets, ARM Powered solutions need to be optimized across a spectrum of energy-efficiency and high-performance targets," said Tom Cronk, executive VP and GM, Processor Division at ARM.

"The companies' collaboration has resulted in the Synopsys Reference Implementations for Cortex-A15 and Cortex-A7 processors. They will enable our customers to more quickly converge on their aggressive design goals, and take advantage of the benefits of big.LITTLE processing and POP IP to address the demands of their target markets."

Configured for ARM Cortex-A15 and Cortex-A7 processors as well as CCI-400 interconnect, the Synopsys Reference Implementations provide tool scripts, a baseline floorplan, design constraints and documentation to serve as an optimized starting point for implementation.

These scripts, built on the widely-used Synopsys tool Reference Methodologies (RMs) and optimized for high-performance cores, leverage Galaxy Platform capabilities such as Design Compiler Graphical physical guidance for improved timing and post-route correlation.

The scripts also leverage IC Compiler technologies, including final-stage leakage recovery for reduced leakage power, data flow analysis for faster floorplan creation and transparent interface optimization for faster top-level closure. They are configured for TSMC 28HPM process technology with ARM Artisan standard cells, memories and ARM POP technology. Designers may further optimize the scripts for their own design goals, processor configurations, process technologies and libraries.

Reference Implementation technology plug-ins for the Synopsys Lynx Design System will enable a full, chip-level production design flow. Synopsys also provides expert professional services to help designers deploy and customize the Reference Implementations to achieve their specific SoC design goals.

The Synopsys Reference Implementation for the Cortex-A7 processor cluster is for a quad-core MPCore configuration, optimized first for energy efficiency, then for maximum speed to provide energy-efficient multi-processing. For high-performance multi-processing within a tight power envelope, the Reference Implementation for the Cortex-A15 processor cluster targets a dual-core configuration, optimized first for performance, then for power.

The CCI-400 interconnect implementation is optimized for the combination of these two processor clusters into a big.LITTLE processing system.

ARM and Synopsys have also collaborated on a reference verification platform for Synopsys Discovery Verification IP, which supports the ARM AMBA 4 ACE protocol and CCI-400 interconnect. With this reference verification platform, verification engineers can rapidly develop highly efficient verification environments for their cache-coherent designs.

"This latest collaboration with ARM continues our long-standing tradition of creating solutions to address our mutual customers' key design challenges," said Antun Domic, senior VP and GM, Implementation Group at Synopsys.

"The Synopsys Reference Implementations for ARM Cortex-A15 and Cortex-A7 processors as well as CCI-400 interconnect take advantage of ARM and Synopsys technologies as well as our high-performance and low-power design expertise to enable designers to achieve optimized SoC performance and power targets on an accelerated timeline."

The 28nm Reference Implementation scripts and documentation for dual-core Cortex-A15 MPCore, quad-core Cortex-A7 and CCI-400 interconnect are available today for Synopsys customers under maintenance who are ARMv7 processor licensees:

Lynx technology plug-ins for these Reference Implementations are planned to be available at the end of April, 2013. The Synopsys Verification IP and Reference Platform for AMBA 4 ACE protocol and CCI-400 interconnect are available today from Synopsys.