Semtech announces availability of best-in-class 51.0 Gbps SerDes for ultra-long-haul apps

CAMARILLO, USA: Semtech Corp. announced the availability of the SMI5026 and SMI5036, its 51.0 Gbps DQPSK Multiplexer and Demultiplexer chipset. The SMI5026 and SMI5036 are specifically designed to increase FEC overhead, enabling a significant improvement in optical transmission reach for ultra-long-haul and submarine optical links.

Both devices are designed with BiCMOS Silicon Germanium process and utilize custom, state-of-the-art ceramic BGA (SMT) packaging technologies, allowing for high reliability, high performance, and reduced costs. The SMI5026 Multiplexer is also fully compatible to and can be used in high data rate BSPK-based coherent transmit solutions.

“The SMI5026 and SMI5036 will enable us to target new submarine and ultra-long-haul links that are now being deployed around the world,” said Sameer Vuyyuru, VP and GM for Semtech’s Advanced Communication Product Group. “Carriers and system vendors can translate our market leading 51.0 Gbps DQPSK data rate into FEC overhead to increase transmission reach and significantly reduce system costs. We continue to work closely with our customers and generate solutions based on their requirements in order to maintain our market leadership position while offering the most complete product solutions for 40 and 100 Gbps in the industry.”

The SMI5026 is a 16:2 Multiplexer with on-chip Clock Multiplier Unit (CMU) and integrated DQPSK Precoder. The input data and clock interface is compatible with OIFSFI5-01.0 and OIF-SxI5-01.0 standards and the device features data-to-date skew adjust, full and half rate CML clock outputs, and an on-chip PRWS error checker and pattern generator.

The SMI5036 is a 2:16 dual Clock and Data Recovery (CDR) Demultiplexer device with integrated DQPSK decoder. The output data and clock interface is compatible with OIFSFI5-01.0 and OIF-SxI5-01.0 standards and the device features independent CDR lock status indicators, a per channel adjustable threshold and sample clock phase, and an on-chip PRWS error checker and pattern generator.