Monday, March 19, 2012

Panasonic develops industry's lowest power consumption chipset of less than 1W for multi-gigabit millimeter wave wireless communication

OSAKA, JAPAN: Panasonic Corp. has developed a chipset for multi-gigabit millimeter wave wireless communication that offers the industry's lowest power consumption of less than 1 Watt by employing a new baseband processing architecture. The new chipset will enable stable interactive communication between various kinds of devices supporting the specification developed by the WiGig Alliance.

Panasonic had previously developed fundamental CMOS circuit technologies for 60 GHz transceiver and modem signal processing circuits, but now an additional radio packet processing block has been integrated as a key block of the chipset. This plays a significant role in accelerating the realization of simple to use high-definition video data sharing/streaming applications for mobile devices.

This chipset can be embedded into mobile devices, such as smartphones, which require less than 1-Watt power consumption. This technology enables the transfer a 30 minute-long compressed high-definition video content to mobile devices within 10 seconds. It also allows the streaming of latency-free high-definition video (for example, instant high-definition display updates in response to user controls on mobile devices) directly from a mobile device onto a big screen TV with real-time performance that surpasses any of the existing technologies today.

With regard to high-speed wireless communication for mobile devices, there is presently no practical solution except for the wireless LAN technology that operates in the 2.4 GHz and 5 GHz frequency bands. In the case of 60 GHz high-speed wireless communication devices, the band range has been employed only by stationary devices, not mobile devices, because wider frequency bands require more power and wider chip surface. Panasonic has already developed the basic 60 GHz band radio technologies for mobile devices. With the technological evolution of mobile devices, however, there arose the need for the integration of packet processing block with low power consumption requirement as well as downsizing of the circuit.

This chipset has the following features:
* This newly developed chipset consists of a 60 GHz transceiver LSI, and a baseband processing LSI with Media Access Control (MAC) packet processing capability. Even when operating at a high data rate of 2.5 Gigabits per second, this chipset is capable of achieving less than 1-Watt of power consumption.
* Transceiver LSI size is reduced by more than 50 percent, compared to the transceiver LSI Panasonic developed earlier, while supporting 9 GHz bandwidth which is allocated as unlicensed spectrum in Japan and Europe in the 60 GHz frequency band.

The chipset is realized by adopting the following new technologies:
* Low power consumption MAC packet processing technology that employs optimum control between general-purpose processor and additional high-speed control circuits to keep processor clock frequency low, thereby achieving less than 1-Watt power consumption performance.
* New high accuracy coil-shaped circuit topology that overcomes the limitation of transistor separation distance requirements for 60 GHz carrier frequency, thereby achieving chip size reduction.

This result was supported in part by the "research and development project for expansion of radio spectrum resources of The Ministry of Internal Affairs and Communications, Japan.

The company holds 36 patents in Japan and 35 patents overseas including pending applications.

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