Si2 to host design for manufacturability (DFM) workshop

AUSTIN, USA: The Silicon Integration Initiative (Si2) announced the Design for Manufacturability Workshop-DFM Challenges at Sub-45nm Design, at the Design Automation Conference (DAC) show to be held at the Moscone Convention Center in San Francisco, CA, from July 26-31, 2009.

The workshop will be held on July 27, from 1PM – 3PM in Room 130 at the Moscone Convention Center. In consideration of today’s economic conditions, Si2 is pleased to offer this workshop free of charge. Attendees can register at the DAC website: http://www.dac.com/46th/onlinereg.html

We have entered an era when the design, manufacturing and test of IP blocks and SoC’s are being done by different companies. The subject of Design for Manufacturability is rushing to the forefront of the list of challenges to the semiconductor and EDA industries.

This workshop will address the current situation in the DFM arena and describe tangible and specific progress in a number of design areas targeted at 45nm and below.

This workshop will present interface standards being developed between chip design and manufacturing flows as well as a clear lexicon that defines most, if not all, manufacturing technology parameters which have heretofore been loosely described and have been often confused among foundries, EDA vendors, and end customers. This includes establishing a clear DFM Terminology and the infrastructure roadmap for standard interfaces between design and manufacturing.

This workshop will showcase the tangible progress that is being made, and demonstrate how interested companies may adopt these results and participate in their continued evolution.

As part of the workshop, selected vendors will present their products and techniques aimed at helping designers produce higher yielding ICs and systems at advanced process nodes. Comparisons of restricted 2D layouts, prescriptive 1D layouts and methods for the integrated analysis and layout optimization will be presented for process nodes from 45nm down to 22nm.

The construction methods, analysis views and the objective functions for multi-goal optimization will be presented by several companies who are enabling high volume production of circuits at 32nm and are now staking out plans for moving down to 22nm.