ChipVision PowerOpt enhances power optimization, C++/SystemC language support

OLDENBURG, GERMANY & SAN JOSE, USA: ChipVision Design Systems, the company whose award-winning, patented PowerOpt™ solution reduces power consumption by up to 75 percent through system-level optimization, announced it has enhanced its PowerOpt solution with major advances in system-level power optimization, increased the synthesis speed to up to 10 times that of competitive tools, and broadened its language support for designs written in ANSI C, C++ and SystemC.

PowerOpt is the only high-level synthesis tool that optimizes design architectures for low power and enables tradeoffs between power, timing and area at the system level. ChipVision will demonstrate the new version of PowerOpt in Booth #3555 at the Design Automation Conference, July 26-31, 2009, in San Francisco.

Many new innovations in PowerOpt bring significant reductions in power consumption in synthesized designs. These innovations include enhanced loop pipelining with automatic run-out support for automatic pipeline flushing; memory access optimizations; and false path elimination and SDC constraint generation, enabling creation of the lowest-power architectures that can be synthesized to gates using RTL synthesis.

New features also include enhanced clock-gating optimization to determine lowest-power configuration on a register-by-register basis, as well as finite state machine (FSM) encoding that minimizes switching activity to reduce power.

PowerOpt now operates with a higher degree of automation within a given constraints space, while still preserving the options for precise user control via its powerful constraint mechanism.

In addition, ChipVision has dramatically increased the synthesis speed of PowerOpt in this version, showing runtimes up to 10 times faster than other available tools. Other enhancements are in the areas of synthesis optimizations, supported synthesis schemes, and usability. Several new synthesis optimizations help to minimize latency and resource usage as well as register lifetimes.

PowerOpt’s synthesis scheme now supports multiple types of blocking and non-blocking communication channels that even allow the transmission of complex data structures over the channels. New Verilog linting support and various new constraints simplify the integration of the synthesized Verilog into existing RTL design environments.

The new version of PowerOpt now also offers broader support for a range of coding styles for ANSI C, C++ and SystemC designs. This means designers can use advanced C++ features such as classes, inheritance, and template functions, and they gain support for SystemC 2.2.

“These new capabilities in PowerOpt have further advanced the state of the art in power optimization,” said Craig Cochran, VP of marketing and business development for ChipVision.

“As the only power-optimizing high-level synthesis tool, PowerOpt has shown significant advantages by addressing power at the system-level before an architecture is determined. Designers in the wireless, graphics, consumer and other power-sensitive segments are showing strong interest in this powerful, unique approach that is winning benchmarks and awards.”