BERNIN, FRANCE & PEABODY, USA: Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, announced its fully depleted (FD) product roadmap comprising two products designed for both planar and three-dimensional (FinFET) approaches to building transistors.
Available now, FD wafers from Soitec, pre-integrate critical characteristics of the transistor within the wafer structure itself. Soitec's FD wafers offer an early, low-risk migration at the 28nm node down to 10nm and beyond, lowering costs and enabling significant advances in the performance and power efficiency of mobile devices such as smartphones and tablets. Soitec also announced research and other activities dedicated to further boosting transistor performance, both silicon-based and with new materials.
Soitec's product lines support the industry's FD International Technology Roadmap for Semiconductors (ITRS), speeding time-to-market and lowering chipmakers' overall manufacturing costs.
Soitec's FD-2D product line enables a unique planar approach to fully depleted silicon technology as early as the 28nm node, in which chipmakers can continue to leverage their existing designs and process technologies. FD-2D also enables immediate gains in performance and energy efficiency for mobile and consumer multimedia chips. The company's FD-3D product line facilitates the introduction of three-dimensional (FinFET) architectures with reduced time and investment, and drives substantial simplifications in the transistor fabrication process, targeting nodes below 20nm.
"Our fully depleted product roadmap addresses the critical needs of the semiconductor industry and solves key challenges facing manufacturers today. Whichever path chip vendors choose to follow - planar or FinFET - Soitec provides solutions that address cost, performance, power-efficiency and time-to-market issues," said Paul Boudre, COO of Soitec. "FD-2D enables immediate and significant performance leaps, while FD-3D makes FinFET a reality for the entire industry at accelerated schedules and reduced risk."
Soitec's proprietary Smart Cut layer transfer technology is leveraged to generate thin layers with high quality and uniformity, bringing the ability to tune starting wafers to successive technology nodes and delivering key advantages as chip manufacturers pursue the best performance, efficiency and manufacturability results.
By predefining critical characteristics of the transistor, these wafers enable efficient implementation and manufacturing. Specifically, they feature a high-quality top silicon layer over a buried isolation layer - these two layers are carefully optimized to predefine the geometry and electrical isolation of transistors, enabling suppression of process steps and simplification of the CMOS fabrication process, opening new usage opportunities and providing a lower-cost solution.