Wednesday, March 14, 2012

Advanced Micro-Fabrication Equipment debuts new etch tool for 3DIC and packaging apps

SHANGHAI, CHINA & SAN FRANCISCO, USA: In a move that extends its market reach and broadens its product portfolio, Advanced Micro-Fabrication Equipment Inc. (AMEC) unveiled the Primo TSV200E - a compact, ultra high-productivity etch tool for 200mm wafer-level packaging, MEMS and 3DIC applications.

Leveraging advanced etch technologies found in AMEC's Primo D-RIE and Primo AD-RIE tools, the new system will be used to build CMOS image sensors, LEDs, MEMS and other devices. Several tools are already deployed in production at Q Technology Limited (Q Tech) and JCAP Corp. (JCAP) in China. The customers are using the tool to support their advanced packaging activities. New orders are expected soon from Taiwan and Singapore.

Three key features differentiate the tool from the competition and make it especially valuable for Through-Silicon-Via (TSV) applications. They include: a dual-station chamber architecture for faster throughput, integrated pre-heat stations for high process reliability and effectiveness, and a unique gas delivery design for better uniformity and higher etch rates. Together, these features give the tool a 30 percent capital-efficiency premium over all other TSV etchers on the market.

The tool represents a natural step for AMEC and puts the Asia-based company at the center of a fast-growing market. Research firm Yole Developpement expects the 3D and wafer-level packaging equipment market to reach $788 million this year. By 2016, the number will soar to $2.4 billion. TSV etchers will account for a large share of the equipment, with strong demand likely to come from China-based companies.

AMEC developed its TSV etcher to meet the demand. 3DICs are essential enablers of the tiny System-on-Chip (SOC) packages that CMOS image sensors, LEDs, MEMS and other devices depend on. The new stacking approach became imperative as transistor feature sizes shrank. The smaller features complicated voltage scaling and forced trade-offs between power and performance. By stacking the die, interconnects are shorter than traditional wire bonding. This enables increased package densities, faster data transfer or processor speed and lower power consumption - all in a smaller form factor.

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