Monday, April 16, 2012

IROC to intro TFIT 2 at IRPS 2012 to allow IC designers to analyze and prevent soft errors at lower geometries

IRPS Conference, ANAHEIM, USA: IROC Technologies, developers of the industry standard for integrated circuit (IC) soft error analysis and prevention, will introduce TFIT 2 at the IEEE International Reliability Physics Symposium (IRPS 2012) in Anaheim, CA from April 15th to 19th.

The company will present the latest functionalities and performance of TFIT 2, with the new soft error rate (SER) response model developed in conjunction with TSMC targeting 28HP process node. TSMC has collaborated with IROC to improve SER for test and simulation. The need for soft error assessment has increased with technology progression, and at 28nm many designers need better tools to perform this task.

TFIT focuses at the cell level on the impact of soft error effects on the reliability and quality of ICs. TFIT 2 lets design engineers be proactive in assessing soft error issues and in optimizing their cell design for improved resilience especially at 65nm and below.

Soft errors are caused by the interaction of natural radiation with silicon. They can happen at any time and at any location during the operational life of the device. The smaller the technology, the higher the sensitivity of designs to soft errors, that cannot be eliminated using classic post-manufacturing reliability techniques such as burn-in or stress test. Typically expressed as the number of failures in time (FIT), the SER for IC design is growing as geometries shrink and now impacts many fabless companies and independent device manufacturers (IDMs).

IROC has been in the soft error business for a decade, developing simulation expertise and tools while also providing test and analysis services. TFIT 2 predicts the SER FIT of any CMOS digital cell. The company’s novel algorithms capture the complexity of cosmic rays interactions with silicon very quickly and accurately, using the cell SPICE netlist and layout as design input, and the transistor model and process response model provided by foundries as technology input. TFIT 2 complements IROC’s circuit level SER assessment tool (SOCFIT) and is used to build a database of FIT rates for each individual cell used in a circuit.

Engineers, even non-SER specialists, find TFIT easy to use as well as very fast and accurate. According to Shi-Jie Wen, distinguished engineer at Cisco Systems: “We benchmarked TFIT with results of tests on silicon for several designs and other tools. The correlation between the simulation results and test is impressive for the TSMC 40nm process node. Cisco is committed to continue our correlation work with TFIT on the other silicon technology nodes. TFIT is one of the best commercially available simulation tools for soft error simulation.”

TFIT 2 uses TSMC process technology characterization for soft errors. As a result, designers can acquire accurate process SER response models in TSMC advanced technology nodes.

"TSMC chose IROC for SER test and simulation to provide customer needs from cell/lib SER assessment, to IC SER simulation and design optimization,” said Ken Chen, senior director, TSMC Business Development. “IROC accurately correlates with TSMC process technology, leading to unique 40nm and 28nm SER solutions and services for TSMC customers."

“Our collaboration with TSMC to characterize their advanced technology process nodes with regard to ionizing particle strikes has helped make TFIT results accurate within 10 percent to 15 percent of test results and very fast,” said Olivier Lauzeral, GM for IROC Technologies. “Our experience with soft error testing, technology trends and design behavior has allowed us to constantly correlate and fine tune TFIT to make it even more accurate.”

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