SAN JOSE, USA: Cadence Design Systems Inc. announced that China's Semiconductor Manufacturing International Corp. (SMIC), one of the world's leading foundries, has introduced a low-power, advanced-node IC design reference flow using Cadence Encounter digital technology and SMIC's 40-nanometer manufacturing process.
This new reference flow offers design teams a predictable and accelerated path to complex SoC designs for a wide range of low-power applications, including the latest consumer electronics products such as tablets and smartphones.
The SMIC-Cadence flow automates designs with advanced power management features. This production-proven methodology is fully incorporated across the complete and integrated Cadence RTL to GDSII flow, which includes Encounter RTL Compiler, Encounter Conformal Low Power, Encounter Digital Implementation System, Encounter Timing System, Encounter Power System, Cadence QRC, Cadence CMP Predictor and Cadence Physical Verification System.
"We have worked closely with Cadence to develop a reference flow that helps our customers accelerate and differentiate their low-power, high-performance chips," said Tianshen Tang, vice president of SMIC Design Service. "By using this interoperable, low-power, Common Power Format-based flow from RTL to GDSII, design teams can achieve faster time-to-volume for advanced low-power 40-nanometer designs."
"Cadence and SMIC have teamed to enable joint customers to benefit from a comprehensive set of digital technologies such as flat power aware implementation with timing and signal integrity closure, power domain aware physical synthesis, closed loop low-power verification and physical verification," said John Murphy, group director, Strategic Alliances at Cadence. "By using this proven flow with the 40-nanometer SMIC manufacturing process, customers have a differentiated approach to low-power design that can get them to market faster with lower power consumption."