AUSTIN, USA: Silicon Laboratories Inc., a leader in high-performance, analog-intensive, mixed-signal ICs, announced the expansion of its PCI Express (PCIe) clock generator and clock buffer portfolio, providing the industry’s broadest range of clocking solutions to address the stringent specifications of the PCIe Generation 1/2/3 standards.
Silicon Labs’ expanded PCIe timing portfolio includes both off-the-shelf Si5214x clock generators and Si5315x clock buffers for power- and cost-sensitive PCIe applications and the Si5335 web-customizable clock generator/buffer for FPGA- and SoC-based designs requiring various differential clock formats that also comply with the PCIe standard.
The PCIe interconnect standard has been widely adopted in numerous applications including consumer electronics, blade servers, storage, embedded computing, IP gateways and industrial systems. The PCIe interface is also supported in FPGA and SoC devices, providing designers with versatile, high-performance solutions for transferring data within systems. Silicon Labs has applied its patented mixed-signal technology to deliver a suite of flexible clocking solutions that enable PCIe design across varying market and application requirements.
“By applying our ‘one-stop-shop’ timing IC supplier model to the PCIe market, we’re providing customers with the utmost flexibility in choosing the right clocking solutions for their PCIe application needs,” said Mike Petrowski, GM of Silicon Labs’ timing products. “Our expanded PCIe timing solution portfolio gives developers a full complement of off-the-shelf options for minimizing power, enhancing signal integrity and reducing cost, as well as the industry’s most customizable clock generators and buffers for FPGA-based designs.”