Fujitsu expands use of Calibre for advanced IC physical verification and design for manufacturing

WILSONVILLE, USA: Mentor Graphics Corp. announced that Fujitsu Semiconductor Ltd has expanded its use of the Calibre platform, incorporating the latest Calibre physical verification and design for manufacturing (DFM) capabilities in its design enabling flow for all Fujitsu Semiconductor projects, including its most advanced analog and digital designs.

The selection was driven by the Calibre product’s industry-leading accuracy and performance, which address design complexity at advanced nodes, as well as new Calibre productivity features. For example, the Calibre platform provides pattern matching for fast identification of litho hotspots and other design rule check (DRC) violations, automatic waivers for managing rule waivers during DRC, programmable electrical rule checking (PERC) for reliability verification, and the SmartFill function to realize advanced timing-aware filling for DFM.

“Exponentially increasing design complexity is something we must consider as we and our customers develop products on more advanced processes,” said Hiroshi Ikeda, director of the System LSI Technology and Design Platform Development Department at Fujitsu Semiconductor. “Our designers need tools that improve designer efficiency and help achieve reduced time-to-market targets. The Calibre platform addresses these needs by making complex design rule checks easier to specify, by tracking waivers automatically, and by automating electrical checks that we have been forced to perform, mostly by hand, in the past. We also believe that the Mentor SmartFill fill solution is needed to achieve faster and less intrusive DFM filling to keep up with more advanced nodes.”

The Calibre Pattern Matching solution provides automatic pattern capturing capability to easily and accurately create multi-dimensional layout verification rules, resulting in a smaller number of rules to be described and shorter verification time. Pattern-based rules also help to speed up the feedback loop when problematic layout patterns are detected during manufacturing and testing.

The Calibre Automatic Waivers system allows information about approved design rule waivers to be included directly in the design database, automatically eliminating spurious DRC violations. This saves designers a significant amount of time because they do not have to debug or re-validate waivers during the implementation process.

The Calibre PERC product enhances overall design reliability by providing a fast verification environment to check design constraints related to electrostatic discharge (ESD), latch-up and other analog design factors that previously had to be checked through visual inspections.

By optimizing fill shapes for multiple objectives and across multiple layers, the Calibre SmartFill tool produces a layout that is more robust with fewer manufacturing and post-fill induced timing issues. Fujitsu Semiconductor and Mentor Graphics are working closely to enhance Fujitsu Semiconductor’s DFM methodology by incorporating the SmartFill tool at advanced process nodes.

“At Mentor we are continuously striving to provide solutions that help our customers address the dual challenges of exploding design complexity and shorter market windows,” said Joseph Sawicki, VP and GM of Mentor Graphics Design-to-Silicon division. “We are pleased that Fujitsu Semiconductor has expanded its use of Calibre to resolve these issues in physical verification and DFM at advanced process nodes.”