SEMATECH and Soitec to advance next-gen transistors and metrology techniques

ALBANY, USA: In an effort that will accelerate the development of next-generation transistors, SEMATECH announced that Soitec, a world leader in manufacturing revolutionary semiconductor substrates for the electronics and energy industries, has joined SEMATECH’s Front End Processes (FEP) and Advanced Metrology Programs.

This partnership aims to foster the development of advanced processes, devices, based on Soitec’s leading-edge silicon-on-insulator (SOI) wafers and other advanced engineered wafers for high-performance, low-power IC applications. The collaboration will also focus on applying SEMATECH’s metrology expertise towards extending current solutions to advanced transistor designs.

SOI wafers are widely used today in fabricating semiconductor devices for applications such as computing, telecommunications, and automotive electronics. Compared to bulk silicon, SOI enables significant improvements in device performance including faster switching speeds for transistors and reduced power consumption while also decreasing manufacturing costs through process simplification. In addition, fully depleted SOI presents advantages in variability control and cost reductions at the 28 nm technology node and beyond.

As a member of SEMATECH’s Metrology and FEP divisions, located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, Soitec will collaborate with SEMATECH’s material and metrology experts and leverage SEMATECH’s activities in advanced metrology, materials, process technology, and device characterization to extend CMOS and high-mobility FinFET technologies. Specifically, SEMATECH and Soitec plan to develop dimensional and films metrology on Soitec’s SOI wafers.

“Due to their expertise in advanced CMOS and FinFET transistor modules, SEMATECH was a natural choice to partner with in developing advanced metrology techniques and device characterization for mobility performance,” said Christophe Maleville, senior VP of Soitec’s Microelectronics Business Unit. “Such collaborative efforts will further help demonstrating our cost-effective performance/power contribution to device and highlight yield solutions that will support our customers in their technology roadmaps.”

SEMATECH’s FEP program is exploring innovative materials, new transistor structures, and alternative non-volatile memories to address key aspects of system-level performance, power, variability, and cost and to help accelerate innovation in the continued scaling of logic and memory applications.

“SEMATECH is pleased to welcome Soitec as a partner,” said Raj Jammy, SEMATECH’s VP of emerging technologies. “Soitec’s expertise in substrate fabrication methodology will complement our own device and process expertise as well as enable us to offer our experience in developing leading-edge metrology capabilities to characterize these advanced devices and evaluate critical defects. We will work together to develop practical and promising high-mobility non-planar and metrology approaches to speed the transition of these new innovations to mainstream semiconductor production.”

SEMATECH’s Advanced Metrology program has developed world-class knowledge of the technologies and methodologies necessary to provide solutions for the measurement needs of high-volume manufacturing. Driven by joint development projects with tool suppliers and leading universities, its goal is to identify key gaps in measurement technology for advanced devices and to develop solutions to meet the needs of the sub-20 nm technology node and beyond.