Yamaha standardizes on Synopsys' processor designer after cutting DSP development time in half

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Yamaha has adopted the Synopsys Processor Designer tool for the development of its custom-designed digital signal processing (DSP) devices.

Using the Processor Designer tool to automate the design and implementation of its XMP-1 DSP, Yamaha doubled the number of sound channels for their high definition sound generator device and taped out six months, or 50 percent, earlier compared to their previous generation device. The design team cited the Processor Designer tool's complete flow, including the generation of an assembler, linker, C-Compiler and instruction-set simulator (ISS), easy-to-use processor description language and optimized RTL output as the differentiating reasons for choosing the tool.

"XMP-1 delivers 32-channel phrase sound generation, AudioEngine™ rich sound effects and LED direct control functionality for amusement or digital consumer applications – a level of functionality not possible with fixed hardware. Processor Designer made the DSP development process easier to attain higher quality," said Morito Morishima, department manager of product development for the semiconductor division at Yamaha.

"With Processor Designer, we doubled functionality for our high definition sound generation DSP, developing it in just one year, including the entire software development tool chain, while reducing cost."

Yamaha's design team found the LISA processor description language of the Synopsys Processor Designer tool easy to use, helping reduce development time by more than 50 percent versus traditional methods. In addition to doubling the number of sound channels in the XMP-1, Yamaha designers were able to reduce the device's silicon size by 20 percent.

The added flexibility of a software-based solution enabled the design team to add new algorithms after initial design completion without compromising quality or extending the design schedule. Processor Designer's generated C-Compiler was a key benefit as well. Given the small size of the project's engineering team and limited schedule, manually developing a C-Compiler would have been nearly impossible.

"Increasingly, companies like Yamaha find that fixed hardware does not provide the flexibility they need to optimize functionality, performance and power for their specific application," said John Koeter, VP of marketing for IP and systems at Synopsys.

"Processor Designer offers not only flexibility through software programmability, but also a highly automated flow that produces the RTL design as well as the software development environment. Yamaha's results demonstrate that designers can achieve the optimal design tradeoffs with reduced risk and development cost."

Processor Designer accelerates the design of both application-specific processors (ASIPs) and programmable accelerators through automated software development tools (assembler, linker, debugger, C-compiler), RTL and instruction set simulator (ISS) generation from a single, high-level specification. ASIPs and programmable accelerators are increasingly essential to support the convergence of multiple functionalities on a single system-on-chip (SoC). This makes them ideal for use in a wide variety of applications including video, audio, security, networking, baseband, control and industrial automation applications.