CAMPBELL, USA: Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company, in the post-layout verification market focused on solutions for nanometer design applications, announced that it is introducing the industry’s first commercial hierarchical 3D extractor, H3D, for post-layout verification. H3D offers hierarchical parasitic extraction, hierarchical netlisting, unlimited capacity, and field-solver accuracy. H3D works with design flows from the leading EDA suppliers.
“Post-layout verification is a major bottleneck in today’s leading edge designs,” said Yuri Feinberg, CEO. “With the introduction of H3D, this bottleneck is removed by providing an accurate extractor that runs with sub-linear performance and delivers a hierarchical output which enables post-layout simulation speed up.”
As a hierarchical extractor, H3D is ideally suited for array-based and repetitive design structures, including memories, FPGAs, and image sensors.
Based on Silicon Frontline’s patented technology, H3D’s extraction performance is sub-linear, which ensures as design size grows extraction performance improves. By providing a hierarchical output netlist, post-layout simulation performance becomes sub-linear when using hierarchical simulators.
H3D hierarchical extraction results are design dependent, but have shown performance improvements from 20-120x when compared to flat extraction.
Built on a Hierarchical Random Walk Algorithm, users have the ability to specify the accuracy required on a net by net or block by block basis. H3D provides unlimited capacity due to its hierarchical extraction and parallelization.
The hierarchical output supports R, C, distributed RC and RCCc.
H3D is shipping early Q3.