SANTA CLARA, USA: Berkeley Design Automation Inc., the nanometer circuit verification leader, announced that Forza Silicon Inc., a fabless semiconductor company specializing in high-resolution, high-speed CMOS image sensors, has selected the company’s Analog FastSPICE Platform for full-circuit verification and block-level characterization.
"The CMOS image sensors we design have tremendous verification challenges," said Daniel Van Blerkom, Ph.D., CTO at Forza Silicon. "We selected AFS because it can handle verification of our CMOS image sensor ICs with nanometer SPICE accuracy on circuit complexities which were impossible in our current verification flow. At the block-level, AFS delivered identical results to traditional SPICE 20x faster in post-layout characterization."
The Analog FastSPICE Platform is the industry’s only unified verification platform for nanometer analog, RF, mixed-signal, and custom digital circuits. The AFS Platform combines foundry-certified nm SPICE accuracy, 5x-10x faster single-core performance than any other SPICE circuit simulator, >10M-element capacity, and the industry’s only comprehensive silicon-accurate device noise analysis.
The AFS Platform is a single executable that uses advanced algorithms and numerical analysis to rapidly solve the original device equations and full-circuit matrix without any approximations. It includes licenses for AFS Nano SPICE simulation, AFS circuit simulation, AFS Transient Noise Analysis, AFS RF Analysis, and AFS Co-Simulation.
"We are excited that Forza Silicon has selected the Analog FastSPICE Platform for their verification and characterization flow," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "The design of high-resolution, high-speed CMOS image sensors requires an accurate and efficient verification flow targeted to the growing complexity of these circuits. Forza's adoption of the AFS Platform is further evidence that leading fabless semiconductor companies specializing in CMOS image sensors select Berkeley Design Automation for nanometer circuit verification."
Wednesday, May 25, 2011
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