DAC 2011, CUPERTINO, USA: Chip Path Design Systems announced details of its Semiconductor IP Chip Design approach. The new approach centers on one common Semantic-IC Specification with the ability to map to multiple implementation styles and understanding of complete project costs.
For the first time, visibility of implementation timelines and costs become visible across ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), and production-ready ASSP (Application Specific Standard Product) devices. This System Level Design paradigm stands to revolutionize how designs are implemented and IC economics are visualized.
Semiconductor IP Design distills into just three main design components: I/O Channels, Subsystems, and NoC (Network-On-Chip). Semiconductor IP (IP) components are then chosen based on requirements and implementation. Specifications can run through a RFQ Compiler (Request-for-Quote) mapping architecture onto ASIC technology choices as well as FPGA devices from various vendors like Xilinx, Altera, Lattice, etc. Finally, the specification can be evaluated against existing ASSP products such as TIs OMAP, Atmel’s microcontrollers, etc. Chip Path’s approach enables tradeoff analysis like never before.
Design projects have volume, time-to-market and cost requirements creating the need for a profitability analysis in any implementation. Chip Path’s approach is the first step in rolling up Electronic Design Automation (EDA) and Semiconductor IP into one project-centric design paradigm, removing barriers between final implementation choices.
One single mappable architectural Semantic-IC Specification defines the design. As 28nm FPGAs enter the market, ASIC and FPGA capabilities are merging but large differences in time-to-market and cost remain. Because of this, designers need to consider choices carefully, understanding all hidden costs.
Prior to Chip Path’s approach, it has been difficult to determine the tradeoffs between part cost, time-to-market, design conversion, free versus pay IP, and millions of dollars in up-front NRE costs against each other. The evaluation of thousands of FPGA devices and thirteen SoCs (Systems-on-Chip), made possible by Chip Path, is set to forever revolutionize how designs are planned, integrated, and implemented.
Chip Path has aggregated extensive databases of models for Semiconductor IP with over 14,000 entries, IC-Technologies from 14nm to 0.35um (13 nodes), and over 9,000 FPGA devices. These databases are at the heart of a very rapid and accurate compilation methodology. Chip Path’s benefit also extends to shortening implementation time with seamless transition to the design phase. Choosing Semiconductor IP is but one aspect; more important is the integration and realization of a product.
“Semiconductor IP is used in all chip designs today,” said CEO George Janac. “We are creating a Cut-and-Paste design methodology based on it. Chip-to-chip I/O Channels, Subsystems, and NoC (Network-on-Chip or Fabrics) are the best implementation abstractions. Design Planning (Floorplanning) is entering the Semiconductor IP level with a dramatic shortening of implementation time and superior results.”
Chip level integration is simplified by moving up to an I/O Channel level of abstraction. Off-chip interfaces are modeled as connectors (PCIe, DDR3, CAN, Interlaken, and about 80 others). Channels are simply collections of IP that go from I/O Connectors to one or more, on-chip bus connectors. Chip Path’s design knowledge is a key component in helping to make IP-based floorplanning a reality.
Chip Path’s on-chip connector based assembly approach enables rapid integration of ASIC and FPGA. Each IP has one or more connectors using protocols like AMBA, AXI4, OCP-IP, Wishbone, Avalon, and only about 8 others. The full Semiconductor IP Methodology defines an IPCN (IP Connection Network) integrating the entire chip. The IPCN has multiple levels, including clock, reset, test, interrupt, point-to-point networks, with the NoC (Network-on-Chip) or Bus-Fabric remaining the central connectivity paradigm. Connectors allow Memory Mapped (MM) or Streamed (ST) interfaces along with point-to-point hookup.
Chip Path’s catalog today contains over 1,200 IP with NoC connectors. With these, chip assembly is simply a process of defining how various connectors talk to each other. Writing machine readable specifications allows automatic connectivity generation. A CPU centric approach helps bring information from each Semiconductor IP to the processors, via the NoC, for creation of address maps driving software development.
Chip Path is making a methodology datasheet available on its website. Registered users can find the datasheet at: http://www.chippath.com/approach/IPCentricDesign. Additionally, tools will be on display at the Design Automation Conference (DAC) from June 5-10 in San Diego, CA.
Shortening time-to-market and cost reduction are major benefits of the Chip Path approach. Semiconductor IP Chip Design gives users visibility like never before. The company has been working with major vendors and key partners to qualify its approach.