MILPITAS, USA: Open-Silicon Inc., a leading semiconductor design and manufacturing company and founding member of the Interlaken Alliance, announced that it has received its 20th ASIC license for the Open-Silicon Interlaken IP core. In addition, the IP has been taped out in 28nm technology and is now silicon proven at 40nm.
"This achievement comes on the heels of a recent competitive Interlaken IP provider acquisition by an FPGA company. We want to highlight the capability of our Interlaken IP, as well as reassure our current and future ASIC customers that we will continue to provide a high quality core and product support," said Jason Pecor, senior product manager at Open-Silicon. "Open-Silicon is presently in development of the next generation IP core in our Interlaken roadmap."
In March 2011, Open-Silicon announced recent updates to the Interlaken IP core, including fully-configurable SerDes lane mapping between the logical and physical SerDes lanes. As Interlaken interfaces are routinely targeting SerDes rates greater than 10Gbps, custom mapping of the logical and physical SerDes lanes provides the flexibility necessary to ease board-level design complexities for very high-speed chip-to-chip serial interfaces.