Aldec delivers 4 MHz design emulator with extensive debugging support

DAC 2011, HENDERSON, USA: Aldec Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, enhances HES (Hardware Emulation Solutions) by expanding its debugging capabilities, ASIC gate capacity and speed of operation.

The new release of HES Design Verification Manager software, DVM 2011.04, supports SCE-MI 2.0 standard and provides 4 MHz emulation speed for designs with 10 million ASIC gates. The new version of DVM automates the entire design setup process, including the insertion of SCE-MI transactors into the user’s design and SCE-MI API functions to interface with the C/C++ model or testbench on the software side.

Significant improvements in dynamic debugging have also been implemented to provide full visibility into the design, visualization of results in a waveform viewer, setup of hardware breakpoints and triggers, and memory viewer/editor.

“Our key objective is to meet the demands of hardware and software teams to co-verify target applications, drivers and OS with the RTL subsystem at multi-MHz speed with extensive debugging capabilities,” said Zbyszek Zalewski, GM of Aldec’s Hardware Division.