Open-Silicon, MIPS, Dolphin achieve ASIC CPU performance of over 2.4GHz in TSMC 40nm

MILPITAS, SUNNYVALE & SAN JOSE, USA: Open-Silicon Inc., MIPS Technologies Inc. and Dolphin Technology announced the successful tapeout of a high-performance ASIC processor at over 2.4GHz under typical conditions.

This achievement, as measured in timing closure against TSMC reference flow signoff conditions, will make this one of the highest frequency ASIC processors ever built, highlighting the companies' industry-leading technologies for building high-performance processor-based systems.

This high-performance ASIC processor is a follow-on test chip to the 65nm, 1.1GHz test chip announced by Open-Silicon and MIPS Technologies at the end of last year.

The device contains a MIPS32 74Kf processor core, a superscalar, out-of-order (OoO) CPU with high-performance integrated Floating-Point-Unit (FPU), DSP Extensions, 32K L1 Instruction & 32K L1 Data Cache memories and on-chip 8K PDtrace memory buffer.

The MIPS32 74K core is a fully synthesizable, licensable IP core with a 15-stage pipeline for achieving maximum frequencies, and is widely used in high-end digital consumer devices, set-top boxes, and home networking solutions. As with the prior 65nm generation design, RTL design was done by MIPS Technologies, and implementation using the Dolphin memories was done by Open-Silicon. TSMC is fabricating the device using its CyberShuttle prototyping program.

To maximize the performance, Open-Silicon utilized its CoreMAX technology for design-specific library augmentation. For this design, 159 new LVt cells, 147 RVt, and 147 HVt cells were created by Open-Silicon to specifically optimize the critical paths inside the MIPS 74Kf core and FPU.

Other advanced physical design techniques included Open-Silicon's experienced processor floorplanning, clock tree synthesis using useful skew, and timing-driven placement optimization. Cadence EDA layout tools were used for physical design.

"The collaboration between Open-Silicon, MIPS Technologies and Dolphin Technology to develop one of the fastest ASIC processors ever built has proven our combined design capabilities and the strength of the model," said Dr. Naveed Sherwani, CEO and president of Open-Silicon.

"Processor performance optimization is a key requirement for next generation derivative SoCs and ASICs. We continue to invest in our processor design capabilities, including the MAX Technologies, to provide customers with the best possible custom silicon."

"Our 74K cores, which are widely licensed for applications in the digital home, broadband, and wireless networking markets, provide the only licensable CPU IP cores with a 15-stage pipeline, and offer the highest single-core performance in our current portfolio," said Sandeep Vij, CEO and president of MIPS Technologies.

"The 74K core was an ideal candidate to demonstrate top-end performance on a 40nm test chip. We're pleased that we were able to achieve over 2.4GHz in our joint effort with Open-Silicon and Dolphin, and believe this achievement compares favorably with frequency results seen on other IP in 40nm, and even 28nm processes."

"Dolphin Technology, a leading provider of Silicon IP for over 16 years, continually strives to help our partners and customers surpass their design targets," said Mo Tamjidi, CEO, Dolphin Technology. "Achieving breakthrough performance at over 2.4GHz in 40nm demonstrates the extensive experience of the teams at Dolphin, MIPS and Open-Silicon."