Netronome to unveil research results on impacts of stateful flow processing on various processor architectures

SANTA CLARA, USA: Netronome, a leading developer of network flow processors, will disclose research results on the impacts of stateful flow processing when implemented on various processor architectures.

Netronome experts will discuss the details of their findings in two sessions at the Linley Tech Processor Conference taking place Sept. 27-28, 2010 at the Doubletree Hotel in San Jose, California, which focuses on processors and related technologies for networking and communications applications.

An increasing number of networking and communications applications require higher-level security processing and stateful packet inspection. The throughput, latency and high-touch computation on millions of simultaneous flows results in far more complex processing. Netronome’s research shows that ordinary cache-based architectures found in multicore processors and pipelined network processors are ill-suited for future designs as networks evolve to 10, 40 and 100 Gbps.

The company’s director of product management, Daniel Proch, a featured presenter at the conference, will present, “Surpassing the Bandwidth Limitations of Cache-Based Architectures,” taking place during Session 5 on Tuesday, September 28 from 9:00 – 11:50 a.m. A Q&A session and panel discussion will follow his presentation.

“As network bandwidths continue to increase at exponential rates, pipeline and cache-based processing strategies are failing to support these throughputs,” said Proch. “My presentation will describe why stateful flow processing is required to support IP-based services and how network flow processors are required to keep pace with increasing network speeds.”

In addition, Netronome’s CEO, Niel Viljoen, will participate in a panel of industry executives that will discuss the benefits and limitations of leading processors in light of complicated requirements of new communications designs. The “Multicore vs. NPU Smackdown!” panel will take place on Tuesday, September 28 from 11:50 a.m. – 12:30 p.m.

“Our research proves that stateful processing of millions of simultaneous flows has significant consequences on legacy processors,” said Viljoen. “This validates the need for a new architecture purposely defined to satisfy the performance, latency, security and deep packet inspection requirements of new communications designs.”

“A tidal wave of new processors has been announced in the past year, but determining which ones offer the features required by new communications systems can seem like a daunting task,” said Joseph Byrne, senior analyst, The Linley Group.

“The Linley Tech Processor Conference is a unique forum for networking-system engineers to discuss these most recent trends in processor design with the leading suppliers of processors and related technology. Attendees have opportunities to talk informally with each other and suppliers to get the personalized information they need to make decisions about their network-system designs.”