NXP's 150 MHz LPC1800 MCU delivers industry's highest ARM Cortex-M3 performance

EINDHOVEN, THE NETHERLANDS & SAN JOSE, USA: NXP Semiconductors N.V. announced the availability of the industry's highest performance ARM Cortex-M3 microcontroller.

The LPC1800 is optimized for low power operation at very low frequencies all the way through to 150MHz maximum performance from either Flash or RAM. This performance provides maximum connectivity and bandwidth options for a wide range of demanding applications.

The flexible dual-bank 256-bit wide Flash memories can be used for concurrent write/read operations, allowing "golden copy" preservation and prevention of reprogramming mishaps, or simply used as a single bank of memory. The LPC1800 also features two new innovative peripherals: a flexible quad-SPI interface and a state configurable timer subsystem.

"The LPC1800 sets a new performance benchmark for ARM Cortex-M3 microcontrollers," said Geoff Lees, vice president and general manager, microcontroller product line, NXP Semiconductors. "What makes the LPC1800 unique is NXP's innovation in reliable, high performance memory architecture and system peripherals."

Designed using NXP's ultra low-leakage 90nm process technology, the LPC1800 offers faster operation, low dynamic power consumption, and proprietary low leakage optimization yielding between 10 and 100 times' reduction in standby modes.

The LPC1800 offers the industry's largest on-chip SRAM for a Cortex-M3 with up to 200KB provided in multiple banks, each with separate bus master access for higher throughput and individual power-down control for low power operation. The dual-bank 1MB Flash architecture provides the highest reliability in-application re-programming, and allows for non-stop Flash operation.

Taking advantage of the rapid adoption of quad-SPI architectures in newer serial Flash memories, NXP is the first to provide a seamless high-speed interface that will connect with virtually all SPI and quad-SPI manufacturers. High-speed interfacing from quad-lane SPI memories at up to 80 Mbps per lane provides for much larger off-chip data and code execution than available from on-chip memories.

The LPC1800's State Configurable Timer Subsystem comprises of a timer array with a state machine enabling complex functionality including event controlled PWM waveform generation, ADC synchronization and dead time control. This timer subsystem gives embedded designers increased flexibility to create user-defined wave-forms and control signals for many applications including power conversion, lighting and motor applications.

Additional peripherals available on the LPC1800 include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware enabled TCP/IP checksum calculation, a high-resolution color LCD controller, and AES decryption including two 128-bit secure OTP memories for key storage. Versions with AES encryption are available on request.

LPC1800 standard features
Standard features on all members of the series include 32 KB ROM containing boot code and on-chip software drivers, eight-channel General-Purpose DMA (GPDMA) controller, two 10-bit ADCs and 10-bit DAC with data conversion rate of 400k samples/s, a motor control PWM and quadrature encoder interface, 4 UARTs, 2 Fast-mode Plus I2C, I2S, 2 SSP/SPI, Smart card interface, 4 timers, windowed watchdog timer, an alarm timer, an ultra-low power RTC with 256 bytes of battery powered backup registers and up to 80 general purpose I/O pins.