Magma delivers hierarchical reference flow for Common Platform alliance’s 32/28-nm low-power process technology

BANGALORE, INDIA: Magma Design Automation announced the availability of a proven hierarchical RTL-to-GDSII reference flow for the Common Platform alliance’s 32/28nm low-power process technology.

This automated, comprehensive solution provides predictable results and reduces development costs for 2-million-instance and larger systems on chip (SoCs) that are manufactured at this advanced process node.

The hierarchical reference design was implemented using Magma’s full RTL-to-GDSII flow and the ARM 32/28-nm LP process libraries; standard cells, memory compilers and GPIO.

This successful design implementation demonstrates that the flow provides key capabilities required to build multi-Vdd low-power SoCs, validates tool and library interoperability and facilitates rapid user adoption through the inclusion of a sample design which can be accessed from Magma or the Common Platform alliance.

This integrated hierarchical RTL-to-GDSII reference flow is based on Magma’s Talus 1.1, Hydra and Talus Power Pro, providing a comprehensive low-power hierarchical solution.

Talus 1.1 is an integrated RTL-to-GDSII implementation solution that performs timing optimization concurrently during routing – rather than sequentially before and after place and route – providing faster overall design closure with better performance and predictability.

Hydra is a hierarchical design planning solution for large systems on a chip (SoCs) and features out-of-the-box reference flows for enhanced ease of use and faster delivery of better floor plans.

Talus Power Pro supports power optimization techniques required in low-power designs, including multiple voltage domains, which enable the optimal tradeoff between performance, area and power, and clock gating for dynamic power reduction. Talus Power Pro supports both the UPF and CPF standards for power intent.

"The Common Platform alliance 32/28-nm process with Gate First High-k Metal Gate (HKMG) technology maximizes power efficiency and transistor scaling while minimizing die size and design complexity,” said Andy Brotman, vice president of Design Infrastructure at GLOBALFOUNDRIES.

“By partnering with Magma to develop and deliver this reference flow, we enable our mutual customers to quickly take full advantage of leading software and advanced process technology to get the best results and time to market for their advanced designs.”

“Magma software is specifically architected to address the complexity, size and power requirements of multimillion-gate ICs targeted at advanced nodes,” said Premal Buch, general manager of Magma’s Design Implementation Business Unit.

"The Magma-Common Platform alliance reference flow will provide designers with additional confidence in their ability to successfully meet the power, performance and turnaround time goals of advanced ICs.”

Magma will feature its reference flows for the Common Platform alliance 32/28-nm LP and 65-nm LPe processes at GLOBALFOUNDRIES’ Global Technology Conference on Sept. 1, 2010 in Santa Clara.

The reference flow is available upon request from IBM, Samsung Electronics, GLOBALFOUNDRIES and Magma.