Xilinx launches first high-density, rad-hard reconfigurable FPGA for space apps

SAN JOSE, USA: Xilinx Inc. has launched the industry's first high-density, rad-hard reconfigurable FPGA for withstanding radiation environments encountered by applications ranging from low earth-orbiting satellites to systems supporting inter-planetary missions.

The off-the-shelf Xilinx Virtex-5QV FPGA offers the industry's highest density, performance and integration capabilities for complex systems that would otherwise require rad-hard ASIC devices with their high development costs and long lead times, or traditional one-time programmable (OTP) solutions.

The unique combination of rad-hard and re-configurability enables a tremendous reduction in risk to critical programs by allowing minimal-cost, last-minute design changes and even redesigns after launch.

"For over 20 years Xilinx has been enabling space systems designs with our rad-tolerant FPGA platforms and Single Event Effects mitigation design methodologies," said Amit Dhir, senior director, Aerospace/Defense & High-Performance Computing Business at Xilinx. "With the Virtex-5QV FPGA we are enabling new and unprecedented applications in FPGAs, bringing to market a platform that utilizes new rad-hard by design technologies paramount in providing radiation hardness, higher density, higher levels of performance and simpler mitigation schemes compared to previous Xilinx devices."

The newest FPGA from Xilinx is one of the many ways Xilinx is addressing the Programmable Imperative that system developers face given the high-cost, and risk, of custom chip development and rigorous demands for higher-performance and integration.

The Virtex-5QV device joins the FPGAs, IP, ISE Design Suite development tools, kits and support that make up Xilinx's Targeted Design Platforms for delivering programmable solutions that help developers avoid the high cost of ASIC development and still meet the performance and integration requirements specific to their markets.

As the world's largest rad-hard reconfigurable programmable logic device, the Virtex-5QV FPGA is well suited to help next-generation space systems push the boundaries for performance and capability in applications such as video display, communications, radar, encryption, packet processing and control.

"The radiation hardened Xilinx Virtex-5 FPGA represents the biggest step ever taken in performance and affordability for space electronics. Our Air Force satellite developers will be able to do more on-board processing using less power than ever before. And, the flexibility of the Virtex-5QV FPGA means that satellite development schedules will be shortened, saving even more money," said Dr. David A. Hardy, associate director, Space Technology, Air Force Research Laboratory's Space Vehicles Directorate, Kirtland Air Force Base, N.M.

The radiation-hardened version of the commercial Xilinx Virtex-5 FPGA was developed under sponsorship by AFRL's Space Vehicles Directorate.

According to Dave Jungkind, director, Business Development at SEAKR Engineering Inc.: "SEAKR has several programs that are base-lining Xilinx devices, but what the new Virtex rad-hard FPGAs will bring is a step function improvement in size, weight, power and performance. SEAKR is investing heavily to bring this game-changing capability to the aerospace market."

High performance FPGAs for demanding requirements of space
The rad-hard features inherent in Virtex-5QV devices are backed by the highest levels of in-beam testing by the Xilinx Radiation Test Consortium (XRTC) and equivalent to millions of device years in space radiation environments.

This means Virtex-5QV FPGAs provide exceptional protection against Single-Event-Upset (SEU), Total Immunity to Single-Event Latchup (SEL), high tolerance to Total Ionizing Dose (TID), as well as data path protection from Single-Event Transients (SET). For example, the Virtex-5QV FPGA configuration memory provides nearly 1,000 times the SEU hardness of the standard cell latches in the commercial device, while configuration control logic and the JTAG controller have been hardened with embedded triple module redundancy.

The new devices are built on the second-generation ASMBL column-based architecture of the proven, industry-leading Virtex-5 family with support in Xilinx's ISE Design Suite. Virtex-5QV devices integrate many of the same hard-IP system level blocks, such as flexible 36-Kbit/18-Kbit block RAM/FIFOs, second generation 25x18 DSP slices, power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, and PCI Express compliant integrated Endpoint blocks.

The Virtex-5QV device offers 130,000 logic cells, 320 DSP Slices supporting fixed and floating point operations, and 836 user I/Os programmable to more than 30 different standards for applications and ease of interfacing to a wide variety of system components. The Virtex-5QV family also provides the industry's first integrated high-speed connectivity solution for space with 18 channels of 3Gbps Multi-gigabit Serial Transceivers for chip-to-chip, board-to-board and box-to-box communication.

The Virtex-5QV device will be sampling in the current quarter with general production availability planned for first half calendar year 2011.