austriamicrosystems celebrates 4th anniversary of 120 V 0.35 um high-voltage CMOS process

UNTERPREMSTAETTEN, AUSTRIA: austriamicrosystems Full Service Foundry business unit announced the fourth anniversary of high volume production of its leading edge 120 V 0.35 um High-Voltage CMOS technology H35. The H35 specialty foundry technology allows the integration of 3.3 V, 5 V, 20 V, 50 V and 120 V NMOS and PMOS devices on a single chip without any process changes.

H35 is the first purely CMOS based High-Voltage foundry process that matches BCD performance and chip sizes at much lower process complexity. Rigorous modularity permits 100 percent reuse of low voltage CMOS design IP. H35 offers fully scalable High-Voltage NMOS and PMOS devices, floating logic libraries as well as a best-in-class power-on resistance.

This makes the 120 V High-Voltage CMOS technology a compelling solution for fabless design houses and IDMs engaged in fields such as sensor interfaces, power over ethernet, motor controllers and a variety of automotive applications.

"The 0.35 um High-Voltage CMOS process has been running for more than four years in high volume production in austriamicrosystems’ state-of-the-art 8-inch wafer fabrication facility. A vast number of foundry customers have benefited from austriamicrosystems’ high-voltage know-how and commitment to provide customers best-in-class analog semiconductor process technology, manufacturing and services.” says Thomas Riener, VP and GM of austriamicrosystems' Full Service Foundry business unit.

“As only three mask levels on top of CMOS are required, it makes the H35 the lowest complexity process in the market. Combined with area and performance optimized devices, H35 is the optimum choice for designing competitive products in a voltage range from 20 V to 120 V.”

For its fully automotive and medical qualified High-Voltage CMOS process H35, austriamicrosystems delivers its industry benchmark design environment (“HIT-Kit”).

The HIT-Kit comes complete with silicon-validated digital libraries, I/O libraries meeting the military ESD and JEDEC latch-up standards with I/O pads designed to surpass 8 kV HBM and 250 mA latch-up immunity, special utilities optimized for High-Voltage CMOS product design and excellent characterized circuit simulation models.