Cadence develops die model enabling comprehensive chip-package

SAN JOSE, USA: Cadence Design Systems Inc. announced that with the assistance of Fujitsu Semiconductor Ltd and Fujitsu VLSI Ltd (hereafter collectively called Fujitsu), Cadence has developed a standardized die model that provides ASIC and MCU designers with a comprehensive chip-package-board co-design solution.

The solution uses Cadence Encounter Power System and Allegro Package Designer, combined with support from third-party package analysis providers, to implement a standard format for die modeling. The newly implemented open format model facilitates data transfer between the chip design and package design environments to ensure seamless integration and consistent analysis.

Until now, only a few proprietary design flows have been able to fully integrate package analysis. The new flow implemented by Cadence can apply to any analysis flow and the end result is a world-class chip-package-board co-design solution for ASIC/MCU customers of semiconductor manufacturers. These customers then could perform system interconnect analysis that includes very precise chip/package electrical characteristics.

“Fujitsu has a longstanding goal of enabling our ASIC/MCU customers with advanced methodologies and technologies to help them be more efficient in their designs. We were excited to see the development of an open format that enables smooth and efficient data transfer between the chip, package and board design environments,” said Akihiro Yoshitake, general manager of IP & Technology Development and Manufacturing Unit, SoC Design Engineering Division at Fujitsu Semiconductor.

“We believe that the end solution lowers the chip-package design risk by efficiently considering interactions between the die and the package. This enables Fujitsu to roll out a world-class chip-package-board co-design solution to our ASIC/MCU customers.”

The chip-package-board co-design solution enables the chip design team to create a die model containing physical and electrical information that can be used to sensitize package analysis. In addition to custom tuning the package for the end application, the solution enables ASIC/MCU users to perform early-stage tradeoffs for PCB design. This methodology allows PCB designers to reduce the bill of materials by analyzing the combined chip-package-board systems interconnect.

“It’s no longer possible to create an ASIC/MCU design without also considering package and board design,” said David Desharnais, group director, product management, at Cadence.

“As discussed in the EDA360 vision, to close the profitability gap, companies must control hardware/software development costs and lower the costs of packaging, manufacturing, and test. Package choices and board-level interconnect decisions have a strong influence on chip design, and vice versa. Our collaboration with Fujitsu, Sigrity and Ansys has produced a new co-design flow that allows chip and package design teams to seamlessly communicate their design decisions for improved quality and faster time to market.”