MoSys tapes out Bandwidth Engine IC for next generation networking apps

SUNNYVALE, USA: MoSys Inc., a leading provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, has successfully taped out its Bandwidth Engine integrated circuit (IC).

This first member of the MoSys Bandwidth Engine family of advanced system solutions will combine MoSys' patented 1T-SRAM® high-density embedded memory with its ultra high-speed 10 Gigabits per second (Gbps) SerDes interface (I/O) technology and an arithmetic logic unit (ALU).

MoSys expects its Bandwidth Engine to enable up to four times the throughput, two to four times the density, up to 40 percent lower power and deliver a system cost savings of up to 50 percent, compared with today’s alternative solutions. MoSys is targeting to deliver first samples in late 2010, with production quantities available in 2011.

“The tape-out of our first Bandwidth Engine IC is a major milestone in MoSys’ transition to a fabless semiconductor company, and I want to congratulate our engineering team on this magnificent accomplishment. We have several prospective customers lined up in the high speed networking and storage markets, and this tape-out is a key first step in bringing the first Bandwidth Engine product to market,” said Len Perham, President and CEO of MoSys.

“We believe that the market for our Bandwidth Engine family of ICs will be substantial and provide a strong foundation for long-term growth and value creation at MoSys.”

For the past several years, processor performance in applications, such as computing and networking, has continued to nearly double every 18 months. During the same period, the performance of today’s system memory technology has not kept pace, creating a significant barrier to improving overall equipment performance.

The Bandwidth Engine family of ICs represents a breakthrough for next-generation networking systems. Combining the high-speed random access of a 1T-SRAM memory core with 16 serial I/O lanes operating at 10 Gbps will enable a Bandwidth Engine device to provide up to two billion accesses per second, which is more than twice the performance of designs utilizing conventional memory technology.

To further boost system performance, the on-chip ALU will allow macro functions to be performed within the Bandwidth Engine, reducing iterations between the other packet processing ICs and the Bandwidth Engine device, the net result of which will be less intra-card electrical traffic, fewer pins, lower power, higher speed and an improved and reduced system cost.